Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Electrical properties of 1.5-nm SiON gate-dielectric using radical oxygen and radical nitrogen

We have developed a low-leakage and highly reliable 1.5-nm SiON gate-dielectric by using radical oxygen and nitrogen. In this development, we introduce a new method for determining an ultrathin SiON gate-dielectric thickness based on the threshold voltage dependence on the substrate bias in MOSFETs. It was found that oxidation using radical oxygen followed by nitridation using radical nitrogen provides the 1.5-nm (oxide equivalent thickness) SiON, in which leakage current is two orders of magnitude less than that of 1.5-nm SiO/sub 2/ without degrading device performance in NMOSFETs. The 1.5-nm (oxide equivalent thickness) SiON was also found to be ten times more reliable than 1.5-nm SiO/sub 2/.     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

CCD栅介质工艺对多晶硅层间介质的影响

CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响.采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响.研究结果表明:栅介质工艺对多晶硅层间介质形貌具有显著的影响.栅介质氮化硅淀积后进行氧化,随着氧化时间延长,靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大.增加氮化硅氧化时间到320 min,多晶硅层间薄弱区氧化层厚度增加到227 nm.在前一次多晶硅氧化后淀积一层15 nm厚氮化硅,能够很好地填充多晶硅层间介质空隙区,不会对CCD工作电压产生不利的影响.     

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.     

Influence of sidewall spacer on threshold voltage of MOSFET with high-k gate dielectric

In this paper, an analytical expression of the gate-dielectric fringing-potential distribution is derived for high-k gate-dielectric MOSFET through a conformal-mapping transformation method for the first time. Based on the fringing-potential distribution, the threshold-voltage model of the MOSFET is improved, and the influence of sidewall spacer on the threshold voltage is discussed in detail. Calculated results indicate that low-k sidewall spacer can alleviate the fringing-field effect.     

Externally Assembled Gate-All-Around Carbon Nanotube Field-Effect Transistor

In this letter, we demonstrate a gate-all-around single-wall carbon nanotube field-effect transistor. This is the first successful experimental implementation of an off-chip gate and gate-dielectric assembly with subsequent deposition on a suitable substrate. The fabrication process and device measurements are discussed in the letter. We also argue in how far charges in the gate oxide are responsible for the observed nonideal device performance.     

High-performance poly-silicon TFTs incorporating LaAlO/sub 3/ as the gate dielectric

We have integrated a high-/spl kappa/ LaAlO/sub 3/ dielectric into low-temperature poly-Si (LTPS) thin-film transistors (TFTs). Good TFT performance was achieved-such as a high drive current, low threshold voltage and subthreshold slope, as well as an excellent on/off current ratio and high gate-dielectric breakdown field. This was achieved without hydrogen passivation or special crystallization steps. The good performance is related to the high gate capacitance density and small equivalent-oxide thickness provided by the high-/spl kappa/ dielectric.     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

Gray-level grouping (GLG): an automatic method for optimized image contrast enhancement--Part II: the variations.

This is Part II of the paper, "Gray-Level Grouping (GLG): an Automatic Method for Optimized Image Contrast Enhancement". Part I of this paper introduced a new automatic contrast enhancement technique: gray-level grouping (GLG). GLG is a general and powerful technique, which can be conveniently applied to a broad variety of low-contrast images and outperforms conventional contrast enhancement techniques. However, the basic GLG method still has limitations and cannot enhance certain classes of low-contrast images well, e.g., images with a noisy background. The basic GLG also cannot fulfill certain special application purposes, e.g., enhancing only part of an image which corresponds to a certain segment of the image histogram. In order to break through these limitations, this paper introduces an extension of the basic GLG algorithm, selective gray-level grouping (SGLG), which groups the histogram components in different segments of the grayscale using different criteria and, hence, is able to enhance different parts of the histogram to various extents. This paper also introduces two new preprocessing methods to eliminate background noise in noisy low-contrast images so that such images can be properly enhanced by the (S)GLG technique. The extension of (S)GLG to color images is also discussed in this paper. SGLG and its variations extend the capability of the basic GLG to a larger variety of low-contrast images, and can fulfill special application requirements. SGLG and its variations not only produce results superior to conventional contrast enhancement techniques, but are also fully automatic under most circumstances, and are applicable to a broad variety of images.     

Gray-level grouping (GLG): an automatic method for optimized image contrast enhancement--Part I: the basic method.

Contrast enhancement has an important role in image processing applications. Conventional contrast enhancement techniques either often fail to produce satisfactory results for a broad variety of low-contrast images, or cannot be automatically applied to different images, because their parameters must be specified manually to produce a satisfactory result for a given image. This paper describes a new automatic method for contrast enhancement. The basic procedure is to first group the histogram components of a low-contrast image into a proper number of bins according to a selected criterion, then redistribute these bins uniformly over the grayscale, and finally ungroup the previously grouped gray-levels. Accordingly, this new technique is named gray-level grouping (GLG). GLG not only produces results superior to conventional contrast enhancement techniques, but is also fully automatic in most circumstances, and is applicable to a broad variety of images. An extension of GLG, selective GLG (SGLG), and its variations will be discussed in Part II of this paper. SGLG selectively groups and ungroups histogram components to achieve specific application purposes, such as eliminating background noise, enhancing a specific segment of the histogram, and so on. The extension of GLG to color images will also be discussed in Part II.     

2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

高k栅介质MOSFETs的二维阈值电压模型

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

Impact of super-steep-retrograde channel doping profiles on theperformance of scaled devices

Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L_gate and the same off-state leakage current I_off, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar     

A 6,13-bis(Triisopropylsilylethynyl) Pentacene Thin-Film Transistor Using a Spun-On Inorganic Gate-Dielectric

We present the latest results of the use of soluble materials such as organic semiconductors (OSCs) or gate-dielectrics for simplified processing of organic thin-film transistors (OTFTs). In this paper, we described our fabrication of a solution-processed OTFT with 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) as the OSC and siloxane-based spin-on glass (SOG) as the inorganic gate-dielectric. Also, synthesized TIPS-pentacene and SOG were examined for use as the OSC and gate-dielectric in an OTFT. From electrical measurements, we obtained device performance characteristics such as charge carrier mobility, threshold voltage, current ON/OFF ratio, and subthreshold swing, which were 6.48 times 10^-3 cm²/V ldr s, -13 V, ~100, and 1.83 V/dec, respectively.     

Graphene flakes at the SiO2/organic-semiconductor interface for high-mobility field-effect transistors

We demonstrate that high-transconductance organic thin film transistors can be achieved by depositing electrochemically exfoliated graphene flakes at the gate-dielectric/organic semiconductor (OS) interface. This effect is applicable to both, solution processed, polymer-based and vacuum-evaporated small-molecule OS-based transistors. Poly(3-hexylthiophene) (P3HT) transistors exhibit a factor of seven higher charge carrier mobility, while pentacene transistors exhibit a fourfold increase in charge carrier mobility, if graphene flakes are present at the dielectric/OS interface.     

A wide bandwidth and wide beamwidth CDMA/GSM base station antenna array with low backlobe radiation

A wide bandwidth and wide beamwidth L-probe-fed patch antenna array with a novel design of grounded structure is proposed and tested. The antenna is made of stacked patches supported by plastic screws. The patches are proximity fed via L-shaped probe. By cutting slots in two vertical side walls of a box-shaped grounded structure, an impedance bandwidth larger than 20% (SWR<1.5), an H-plane beamwidth over 90/spl deg/, and much reduction in backlobe radiation can be obtained. Details of the proposed antenna, simulation, and experimental results are presented and discussed.     

Improving the quality of sub-1.5-nm-thick oxynitride gate dielectric for FETs with narrow channel and shallow-trench isolation using radical oxygen and nitrogen

We have demonstrated that oxynitridation using radical-oxygen (radical-O) and radical-nitrogen (radical-N) improves reverse narrow channel effects (RNCE) and reliability in sub-1.5-nm-thick gate-SiO/sub 2/ FETs with narrow channel and shallow-trench isolation (STI), suitable for high-density SRAM and logic devices. The STI formation followed by oxidation for the gate-dielectric causes various orientations of the Si surface, and thus, thermal oxidation forms the partial thin SiO/sub 2/ and causes RNCE and reliability degradation. Oxidation using radical-O forms uniform SiO/sub 2/ on Si[100] and Si[111] surfaces and suppresses RNCE in a sub-1.5 nm-thick gate-SiO/sub 2/ FET with STI. Nitrifying the SiO/sub 2/ using radical-N increases the physical thickness while maintaining the oxide equivalent thickness on both Si[111] and Si[100] surfaces, thus producing a low-leakage and highly reliable sub-1.5 nm-thick gate-SiON.     

电流增益截止频率为236GHz的InAIN/GaN高频HEMT

研制了高电流增益截止频率(fT)的InAlN/GaN高电子迁移率晶体管(HEMT).采用金属有机化学气相沉积(MOCVD)再生长n+GaN非合金欧姆接触工艺将器件源漏间距缩小至600 nm,降低了源、漏寄生电阻,有利于改善器件的寄生效应;使用低压化学气相沉积(LPCVD)生长SiN作为栅下介质,降低了InAlN/GaN HEMT栅漏电;利用电子束光刻实现了栅长为50 nm的T型栅.此外,还讨论了寄生效应对器件fT的影响.测试结果表明,器件的栅漏电为3.8 μA/mm,饱和电流密度为2.5 A/mm,fT达到236 GHz.延时分析表明,器件的寄生延时为0.13 ps,在总延时中所占的比例为19％,优于合金欧姆接触工艺的结果.