异步式逻辑保障片上网络传输可靠性的研究

随着Si技术的持续发展,片上系统(SoC)的规模和复杂度的增长给传统的片上互连,如总线结构,带来了前所未有的挑战。片上网络[1-2]是片上系统的一种新设计方法,是目前公认应对这种挑战较为有效的解决方案。半导体工艺进入深亚微米时代后,片上网络的可靠性也越来越成为人们关注的问题。将在研究如何应用异步式逻辑保障片上网络互连数据传输的可靠性和服务质量,提出了一个异步式片上网络的架构。通过实验证明,异步式逻辑将极大提高集成电路在应对电源不稳定性、导线间串扰、电磁干扰(EMI)、时钟偏斜和软错误方面的可靠性。采用全局异步局部同步的时钟机制,该方法带来了一种全新的片上通信方法,显著改善了传统总线式系统的性能。     

一种片上网络路由器的测试方法

本文在总结片上网络多播测试方法的基础上,针对多播测试方法的缺陷提出了两种改进的片上网络路由器的测试方法。实验证明,这两种改进的方法较多播测试方法减少了测试时间和测试包数,且随着芯片规模的增大,这种优势越明显。在两种改进的方法中,方法2比方法1所需的测试时间更少。     

Scalable connection-based flow control scheme for application-specific network-on-chip

In this paper,a scalable connection-based flow control scheme is proposed for application-specific network-on-chip(NoC).The proposed scheme exploits two distinctive characteristics of NoC,namely traffic predictability and abundant wire resource,to achieve significant performance enhancements.First,the burst injection data are regulated into constant data streams and a connection-based method is used to ensure that all links are not overloaded at any time.Consequently,the number of packets in the network is decreased,leading to a reduced congestion probability and improved communication performance.Second,a simple architecture of the central controller is proposed to guarantee that the proposed scheme has small area overhead and is scalable.Simulation results show that compared with traditional switch-to-switch(STS) flow control scheme and pre-allocation based flow control schemes,the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area and energy overhead.     

片上网络拓朴优化:在离散平面上布局与布线

微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基础通信架构的微系统芯片称为片上网上系统芯片(System-on-Network-on-Chip,SoNoC).微系统芯片内通信模式兼有随机性和确定性,应该根据特定应用的通信特征设计片上网络.本文在确定SoNoC设计流程的基础上,根据SoNoC的通信特征,选择了合适的离散平面结构,对SoNoC的运算及控制等模块进行布局、对模块间的通信依赖关系进行布线,发展出FRoD(Floor-plan and Routing on Discrete Plane)算法,以自动生成片上网络的拓扑结构.该算法定义了离散平面的一般表示方法,并在四种典型的离散平面上使用不同规模的随机系统完成了系列实验.为了处理系统和网络之间的耦合关系,逐点分裂的布局算法可以逐步学习和适应系统的通信需求,同时优化系统的执行时间和通信能量,在运行随机任务流图的模拟系统上与随机布局结果相比可以节省30%左右的通信能量,20%左右的系统通信时间.串行、并行和串并混合的布线算法使用最短路径把通信关系分布在离散平面的通道上,使不同的通信关系尽量复用网络通道,与全连接网络相比可以节省10%到30%的面积代价.     

A new FIFO for transferring data between two unrelated clock domains

A new simple-to-design FIFO that allows data transfer between two clock domains of unrelated frequencies has been developed. The fully synchronous interfaces significantly ease the system-on-chip integration process. With a relatively low gate count, the proposed FIFO allows the producer and consumer to put/get data at their respective frequencies (1?datum/clock cycle) till it gets filled, then the rates converge to the lower of the two frequencies. The maximum initial latency is three cycles of the consumer's clock. Several manifestations of the FIFO have been developed for different design cases including producer/consumer data width mismatch. Operation of the FIFO has been verified using both gate-level simulations and SPICE simulations with a 0.13?µm, 1.2?V technology. An 8-cell FIFO showed proper operation at producer and consumer clock frequencies of 2 and 3.125?GHz, respectively, with a data transfer rate of more than 2?giga datum/s and an average power of 721?µW.     

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits

This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding a priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.     

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.     

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling

The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach. The research is supported by the Swedish Foundation on Strategic Research (SFS) under the Strategic Integrated Electronic Systems Research (STRINGENT) program.     

层次化片上网络结构的簇生成算法

半导体工艺的发展及嵌入式电子产品复杂度的不断增长,系统芯片互连结构的吞吐量、功耗、信号完整性、延迟以及时钟同步等问题更加复杂.基于总线的片上通信结构不足以提供良好的通信能力,出现了以片上网络为核心的通信结构.本文提出了层次化片上网络设计中,根据实现工艺和应用需求,进行层次划分的簇生成算法.实验表明,通过使用该算法,能够有效的分配系统芯片的内部通信,提高系统性能,降低硬件实现开销,同时满足一定的服务质量需求.     

机动通信网分级分布式网络规划设计

为提高机动通信网络规划的科学性、准确性,充分发挥指战员能动性和通信装备效能,提出了一种分级分布式网络规划方法,阐明了分级资源管理和分级分布式网络规划两种应用模式。所提方法支持规划任务的分解和资源段的下发,并能融合各级规划结果,形成全网规划态势。此外,对分布式数据融合过程中必然会出现的冲突设计了检查及处理流程,并根据引起冲突的资源类型,明确了判定规则和处理办法。     

数据采集系统的多机分级通信

针对大容量数据采集系统与计算机之间通信问题,提出分级通信模式,重点介绍了该模式的硬件构成和软件设计,本系统已投入实用,效果良好。     

基于FPGA的片上系统的无线保密通信终端

本系统设计了一种基于Xilinx Spartan 3E FPGA片上系统的无线加密通信终端,充分应用了软硬件编程的优势,实现了基于硬件描述语言VHDL的硬件AES加解密和使用软核MicroBalze来实现流程控制、无线通信、帧结构处理和人机交互,经验证能高速有效地实现保密通信     

基于CAN与485总线的煤矿通信网络设计

针对煤矿井下安全,设计了一种适用于井下矿用保护系统的通信网络。系统的网络结构,采用485总线实现井下各工作通信节点互连、自动地址分配、节点数量查询、线路故障自检等功能。采用CAN总线对已分配地址的输入输出模块节点通信进行井下环境监控,同时增加中继实现远距离通信。该网络系统具有通信节点接入灵活、地址自动分配等特点,适用于井下矿用保护系统。     

访存与用户行为敏感的MPSoC应用映射

应用映射是MPSoC设计中的关键问题,针对多应用负载的MPSoC,提出一种访存与用户行为敏感的动态映射策略,该策略根据应用的数据访问特征区分热点与非热点应用,并对用户行为进行建模,根据用户行为模型,进一步在运行时区分关键与非关键应用.对每个进入系统的应用,按照应用的热点及关键性分类动态选择在线映射算法,让热点应用围绕存储器布局,非热点应用尽量避免占用存储器附近的资源;对关键应用,最小化应用内通信开销和链路竞争,对非关键应用,最小化应用间通信开销和链路竞争.实验表明,与单纯考虑访存或用户行为的映射策略相比,本文策略能够降低系统整体的通信能耗.     

分布式实时通信网络在火控系统中的应用

通过对现代雷达火控系统通信基本特点的分析，提出一种适合于现代雷达火控系统的通信方式——基于ARCNET的多总线拓扑强容错令牌总线网，并对实时系统与实时通信的特征作了深入的分析。     

一种改进的层次化SOCs并行测试封装扫描单元

 测试封装是实现SOC内部IP核可测性和可控性的关键,而扫描单元是测试封装最重要的组成部分.然而传统的测试封装扫描单元在应用于层次化SOCs测试时存在很多缺点,无法保证内部IP核的完全并行测试,并且在测试的安全性,功耗等方面表现出很大问题.本文提出一种改进的层次化SOCs测试封装扫描单元结构,能够有效解决上述问题,该结构的主要思想是对现有的扫描单元进行改进,实现并行测试的同时,通过在适当的位置增加一个传输门,阻止无序的数据在非测试时段进入IP核,使得IP核处于休眠状态,保证了测试的安全性,实现了测试时的低功耗.最后将这种方法应用在一个工业上的层次化SOCs,实验分析表明,改进的测试封装扫描单元比现有扫描单元在增加较小硬件开销的前提下,在并行测试、低功耗、测试安全性和测试覆盖率方面有着明显的优势.     

突飞猛进的光通信技术

随着ＭＰＬＳ、ＤＷＤＭ、数字包封、波长选路及ＷＤＭ保护环网等新技术的开发,ＷＤ Ｍ光网络层已具有许多原先只能在高层实现的网络功能。原先单纯为了增加系统传输容量的ＷＤＭ技术,已转化为具有真正联网功能的多波长光网络技术,为彻底抛弃ＳＯＮＥＴ／ＳＤＨ,直接在具有光联网功能的 ＷＤＭ多波长光网络上承载 ＩＰ业务创造了条件。     

一种基于BFT型拓扑结构片上网络低费用测试方法

随着集成电路制作工艺的进步,多核与众核系统是片上系统的发展趋势.传统的二维网格(2D-mesh)型拓扑结构通信效率低、功耗高和时延长等缺点变得越来越明显.本文首先分析对比了几种常用拓扑结构在多核与众核情况下的性能,进而采用布线复杂度较低、性能较好的蝴蝶型胖树(BFT)拓扑结构来解决片上系统的设计和测试问题.随后,本文针...     

多核系统中NoC通讯架构的关键技术

多核处理器已经成为处理器的主流,并发展成为各种通信与媒体应用的主流处理平台。通讯结构是多核系统中的核心技术之一,核间通信的效率是影响多核处理器性能的重要指标。目前有3种主要的通讯架构:总线系统结构、交叉开关网络和片上网络。总线结构设计相对方便、硬件消耗较少、成本较低;交叉开关是适合用于构建大容量系统的交换网络结构;而片上网络是更高层次、更大规模的片上网络系统,目前可以解决多核体系结构问题,是多核系统最有前途的解决方案之一。文中在分析了NoC结构的基本原理、系统结构和功能的同时,也提供了部分单元的设计实现。