A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.     

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

Design method for fully integrated CMOS RF LNA

An efficient method for fully integrated RF CMOS LNA design is presented. A particular input matching topology enables inductor values to be selected in order to be integrated fully and to minimise the input losses. Moreover, an active device sizing method is used to achieve a 50 /spl Omega/ input impedance with a low noise factor. Simulations show a 3.0 dB noise figure at 2.45 GHz for a power consumption of 10 mW in a 0.28 /spl mu/m RF CMOS process.     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

A fully integrated CMOS receiver front-end for optic GigabitEthernet

A fully integrated fiber-optic receiver chip in a CMOS technology is presented. The design was done in a low-cost mixed-signal analog pure CMOS technology with 0.35-μm gate length. It incorporates every building block needed for standard fiber-optic receiver application, e.g., transimpedance amplifier, postamplifier, signal detect, and several control circuits. The chip works without any external components, such as capacitors usually needed to ensure the broadband operation down to several tens of kilohertz. Three designs were processed for typical data applications between 155 Mb/s and 1.25 Gb/s. The difference in the designs can be created by changing only one metal mask and programming some bandwidth and noise-relevant components on the chip. The results in sensitivity, dynamic range, and other behaviors are fully compliant with the relevant standards, such as SONET or IEEE 802.3 (Gigabit Ethernet) and future IEEE 1394 plastic optical fiber (POF) communication     

A fully integrated CMOS PM radio receiver for wristwatchcalibration

In this paper, a fully integrated phase modulation radio receiver ASIC is presented. The ASIC is a mixed analog and digital circuit, implemented in a 1.5-μm CMOS technology. The only required external components are the reception antenna and a 32-kHz crystal. The radio receiver is dedicated to the 162-kHz “Allouis” radio transmitter. In addition to the audio information, 40-bit/s digital data are transmitted as phase modulation of the main carrier. These digital data may contain “live” information, such as the exact time. The presented ASIC demodulates and decodes these digital data. The principal features of this radio receiver are a low voltage supply (2.2-4.5 V), low power consumption (less than 150 μA), a large sensitivity range (10 μV-100 mV), and a reduced number of external components. Thanks to all of these performances, the circuit can be built in a wristwatch     

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of −95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of −76 and −79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

A low-power multi-band CMOS RF receiver front-end for ubiquitous sensor network applications

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.     

一种新颖全差分光电集成接收机的标准CMOS实现

提出一种新颖的全差分光电集成接收机,它包含了全差分光电探测器和相应的差分接收电路,其中全差分光电探测器的作用是实现入射光信号到全差分光生电流信号的转换.采用特许3.3 V、0.35μm标准CMOS工艺,实现了一种相应的宽带、高灵敏度全差分光电集成接收机.测试结果表明:对于850 nm的入射光,集成全差分光电探测器的差分跨阻前置放大器(TIA)的工作速率可达到500 Mbit/s,而整个光接收机的带宽则达到了1.098 5 GHz;在10-12的误码率条件下,灵敏度可达到-12.3 dBm.     

消费和工业应用中的低功耗考量

消费和工业市场要求在新产品设计中提高能源效率.便携产品需要新一代技术来延长电池使用寿命,而大型产品(如白色家电)则需要提高能源效率来保持竞争优势.很多情况下,利用电子组件替换机械组件可以降低板卡功耗,附加的软件控制能够精确调整应用的功率性能.     

Low-power/low-voltage RF microsystems for wireless sensors networks

This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.     

A micropower CMOS, direct-conversion, VLF receiver chip formagnetic-field wireless applications

A micropower CMOS, direct-conversion very low frequency (VLF) receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, phase locked loop (PLL)-synthesized receiver covers a frequency range of 10-82 kHz and provides both analog and 9-b digital baseband I and Q outputs. Digital I and Q outputs are accumulated in a companion digital chip which provides baseband signal processing. Emphasis is plated on the receiver micropower RF preamplifier which uses a lateral bipolar input device because of the significant increase in flicker noise illustrated for PMOS devices in weak inversion. Lateral bipolar transistors are also utilized in the mixer and IF stages for low flicker noise and low dc offsets. Special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 μV noise floor in 300 Hz BW), and local oscillator feedthrough is indiscernible in the RF preamplifier output noise spectrum. The 100% duty-cycle receiver, intended for miniature, battery-operated wireless applications, operates approximately four months at 80 μA from a 6-V, 220-mA-hr battery     

A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers

A fully integrated differential low-power low-noise amplifier (LNA) for ultrawideband (UWB) systems operating in the 3-5-GHz frequency range is presented. A two-section LC ladder input network is exploited to achieve excellent input match in a wideband fashion and to optimize the noise performance. Prototypes fabricated in a digital 0.13-/spl mu/m complementary metal oxide semiconductor technology show the following performance: 9.5-dB peak power gain, 3.5-dB minimum noise figure, -6-dBm input-referred 1-dB compression point, and -0.8-dBm input-referred third-order intercept point, while drawing 11mA from a 1.5-V supply. The realized LNA is compared with previously reported LNAs tailored for the same frequency range.     

Image-rejection receiver using on-chip active notch filters for 2.4-GHz band wireless communication applications

This paper presents the design and experimental results of image-rejection (IR) receiver front-end for 2.4-GHz band applications. The proposed IR-receiver front-end integrates a third-order active notch filter into each of conventional cascode low noise amplifier and down-conversion mixer to achieve high image-rejection ratio (IRR). The image signal is suppressed and the wanted signal is maximized due to series and parallel resonator effects of the notch filter, respectively. Consequently, the proposed IR-receiver front-end implemented in a standard 0.18 μm CMOS technology has the power gain of 21.5 dB, the noise figure of 3.5 dB, the input third order intermodulation product of ?15 dBm and the IRR of 56 dB. The IR-receiver front-end dissipates a total of 5.5 mA from supply voltage of 1.8 V.     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.