基于RHBD技术CMOS锁存器加固电路的研究

对基于RHBD技术CMOS D锁存器抗辐射加固电路设计技术进行了研究,并对其抗单粒子效应进行了模拟仿真.首先介绍了基于RHBD技术的双互锁存储单元(DICE)技术,然后给出了基于DICE结构的D锁存器的电路设计及其提取版图寄生参数后的功能仿真,并对其抗单粒子效应给出了模拟仿真,得出了此设计下的阈值LET,仿真结果表明:基于DICE结构的D锁存器具有抗单粒子效应的能力.     

32nm CMOS工艺三点翻转自恢复锁存器设计

CMOS工艺的特征尺寸不断缩减,电荷共享效应诱发的单粒子三点翻转成为研究热点.本文提出了一种单粒子三点翻转自恢复的抗辐射加固锁存器:Hydra-DICE(Dual Interlocked Storage Cell).该锁存器基于24个同构的交叉耦合单元(Cross-Coupled Elements,CCE)排列成阵列结...     

一种低开销的三点翻转自恢复锁存器设计

随着集成电路特征尺寸的不断缩减,在恶劣辐射环境下,纳米级CMOS集成电路中单粒子三点翻转的几率日益增高,严重影响可靠性。为了实现单粒子三点翻转自恢复,该文提出一种低开销的三点翻转自恢复锁存器(LC-TNURL)。该锁存器由7个C单元和7个钟控C单元组成,具有对称的环状交叉互锁结构。利用C单元的阻塞特性和交叉互锁连接方式,任意3个内部节点发生翻转后,瞬态脉冲在锁存器内部传播,经过C单元多级阻塞后会逐级消失,确保LC-TNURL锁存器能够自行恢复到正确逻辑状态。详细的HSPICE仿真表明,与其他三点翻转加固锁存器(TNU-Latch, LCTNUT, TNUTL, TNURL)相比,LC-TNURL锁存器的功耗平均降低了31.9%,延迟平均降低了87.8%,功耗延迟积平均降低了92.3%,面积开销平均增加了15.4%。相对于参考文献中提出的锁存器,LC-TNURL锁存器的PVT波动敏感性最低,具有较高的可靠性。     

一种低功耗低延迟的容忍DNU锁存器设计

随着集成电路器件特征尺寸的进一步减小,锁存器内部节点之间的距离越来越短.由于内部节点间的电荷共享效应,器件在空间辐射环境中频繁发生单粒子翻转(SEU),受影响节点由单节点扩展到双节点.文章提出了一种新型的锁存器加固结构,利用C单元固有的保持属性,实现对单节点翻转(SNU)和双节点翻转(DNU)的完全容忍.HSPICE仿...     

一种低开销的三点翻转自恢复锁存器设计

随着集成电路特征尺寸的不断缩减,在恶劣辐射环境下,纳米级CMOS集成电路中单粒子三点翻转的几率日益增高,严重影响可靠性.为了实现单粒子三点翻转自恢复,该文提出一种低开销的三点翻转自恢复锁存器(LC-TNURL).该锁存器由7个C单元和7个钟控C单元组成,具有对称的环状交叉互锁结构.利用C单元的阻塞特性和交叉互锁连接方式,任意3个内部节点发生翻转后,瞬态脉冲在锁存器内部传播,经过C单元多级阻塞后会逐级消失,确保LC-TNURL锁存器能够自行恢复到正确逻辑状态.详细的HSPICE仿真表明,与其他三点翻转加固锁存器(TNU-Latch,LCTNUT,TNUTL,TNURL)相比,LC-TNURL锁存器的功耗平均降低了31.9％,延迟平均降低了87.8％,功耗延迟积平均降低了92.3％,面积开销平均增加了15.4％.相对于参考文献中提出的锁存器,LC-TNURL锁存器的PVT波动敏感性最低,具有较高的可靠性.     

基于DICE结构的SRAM抗辐照加固设计

存储单元的加固是SRAM加固设计中的一个重要环节。经典DICE单元可以在静态情况下有效地抗单粒子翻转,但是动态情况下抗单粒子翻转能力较差。提出了分离位线的DICE结构,使存储单元在读写状态下具有一定的抗单粒子效应能力。同时,对外围电路中的锁存器采用双模冗余的方法,解决锁存器发生SEU的问题。该设计对SRAM进行了多方位的加固,具有很强的抗单粒子翻转能力。     

0.18μm工艺下单粒子加固锁存器的设计与仿真

在近年国际上出现的两种记忆单元DICE（DualInterlockedstoragecell）和GDICE（DICEwithguard—gates）基础上，设计了两种抗单粒子加固锁存器，称为DICE锁存器和GDICE锁存器，加工工艺为0.18μm。对这两种锁存器的改进减少了晶体管数量，降低了功耗，增强了抗单粒子瞬态（singleeventtransient，SET）能力。分别对比了两种锁存器的优缺点。建立了一种单粒子瞬态仿真模型。将该模型连接到锁存器的敏感点．仿真测试了这两种锁存器的抗单粒子翻转（singleeventupset，SEU）能力，得到一些对版图设计有意义的建议。通过比较得知：如果没有特殊版图设计，在单个敏感点被打翻时，DICE锁存器和GDICE锁存器的抗单粒子翻转能力比较强：而在两个敏感点同时被打翻时，抗单粒子翻转能力将比较弱。但如果考虑了特殊版图设计。那么这两种锁存器抗单粒子翻转的优秀能力就能体现出来。     

一种新颖高效抗SEU/SET锁存器设计

随着工艺技术的发展,集成电路对单粒子效应的敏感性不断增加,因而设计容忍单粒子效应的加固电路日益重要.提出了一种新颖的针对单粒子效应的加固锁存器设计,可以有效地缓解单粒子效应对于电路芯片的影响.该锁存器基于DICE和C单元的混合结构,并采用了双模冗余设计.SPICE仿真结果证实了它具有良好的抗SEU/SET性能,软错误率比M.Fazeli等人提出的反馈冗余锁存器结构减少了44.9%.与经典的三模冗余结构比较,面积开销减少了28.6%,功耗开销降低了超过47%.     

基于三模冗余结构的自刷新寄存器设计

设计了一种带自刷新功能的寄存器,该寄存器采用两级数据锁存结构,在第二级锁存结构中设计了一个选择电路。该选择电路采用三选二机制,用于三模冗余结构中取代常用寄存器,选择数据来自三模冗余结构的三路输出。有两路值相同,输出结果为该值,用于修正寄存器的输出值。在0.13μm工艺条件下用此结构设计的寄存器,面积为32.4μm×8.4μm,动态功耗0.072μW·MHz-1,建立时间0.1 ns,保持时间0.08 ns。该结构用于三模冗余结构中,可有效防止单粒子翻转效应(Single Event Upset,SEU)的发生。测试结果表明采用该结构的寄存器组成的存储单元三模冗余加固结构,在时钟频率1 GHz时,单粒子翻转错误率小于10-5。     

单粒子翻转加固锁存器分析与辐照试验验证

对目前基于软错误屏蔽、施密特触发及双互锁单元结构的几种单粒子翻转加固锁存器进行分析,并从面积、延时、功耗和抗单粒子翻转能力等方面进行综合比较。着重剖析了DICE结构的多节点翻转特性,研究了敏感节点隔离对抗单粒子翻转能力的影响,设计了测试芯片,并进行了辐照试验验证。辐照试验结果表明,相比于其他加固锁存器结构,DICE结构的单粒子翻转阈值最高,翻转截面最低,功耗延时积最小。当敏感节点隔离间距由0.21 μm增大到2 μm时,DICE结构的单粒子翻转阈值增大157%,翻转截面减小40%,面积增大1倍。在DICE结构中使用敏感节点隔离可有效提高抗单粒子翻转能力,但在具体的设计加固中,需要在抗辐照能力、面积、延时和功耗之间进行折中考虑。     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

一种低开销的抗SEU锁存器

随着微电子技术的不断进步,集成电路工艺尺寸不断缩小,工作电压不断降低,节点的临界电荷越来越小,空间辐射引起的单粒子效应逐渐成为影响芯片可靠性的重要因素之一。针对辐射环境中高能粒子对锁存器的影响,提出了一种低开销的抗SEU锁存器(LOHL)。该结构基于C单元的双模冗余,实现对单粒子翻转的防护,从而降低软错误发生的概率。Spice模拟结果显示,与其他相关文献中加固锁存器相比,LOHL在电路面积、延迟和延迟-功耗积上有优势。     

SEU/SET加固D触发器的设计与分析

针对D触发器的抗单粒子辐射效应加固,提出了一种新型的保护门触发器(GGFF)设计,使用两个保护门锁存器串接成主从触发器.通过Spice仿真验证了GGFF抗SEU/SET的能力,通过比较和分析,证明GGFF对于具有同样抗SEU/SET能力的时间采样触发器(TSFF),在电路面积和速度上占据明显优势.     

An SEU resilient,SET filterable and cost effective latch in presence of PVT variations

This paper presents a single event upset (SEU) resilient, single event transient (SET) filterable and cost effective latch (referred to as RFEL) using 45 nm CMOS commercial technology. By means of triple mutual feedback CMOS structures, one of which is an input-split Schmitt trigger, and two of which are Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset regardless of the energy of a striking particle. The latch filters a much wider spectrum of single event transient on account of hysteresis property of the embedded input-split Schmitt trigger, and temporal redundancy in the grouped inputs of the Muller C-element at output stage. The latch performs with lower overheads regarding area, power, and delay than most of the single event upset and single event transient simultaneously tolerated latches as well. Simulation results show that the area-power-delay-pulse product of the latch is 65.58% saving on average, and Monte Carlo simulation results demonstrate the equivalent or even less sensitivity of the latch to process, and temperature variations, compared with the previous radiation hardened latches.     

Radiation Hardened by Design Latches — A Review and SEU Fault Simulations

There are many Radiation Hardened by Design (RHBD) architectures presented in the literature to mitigate Single Event Upset (SEU) in a storage element, a latch. Nevertheless, the design of a SEU hardened latch is being continuously improved with respect to reliability, performance, power consumption and area overhead. SEU mitigating techniques by design focus on reducing criticality of sensitive nodes in a latch. Sensitive node(s) in a latch could be an active and/or a high impedance node(s). In this paper, we have classified previously presented SEU hardened by design latch architectures and reviewed SEU mechanisms in selected RHBD latch architectures on Complementary Metal Oxide Semiconductor (CMOS) technology models. Simulation studies using latest fault simulation model have been carried out. Simulation results have revealed some interesting observations described in this paper. Our findings, based on analyses, will provide valuable design inputs for futuristic RHBD latches with advanced technology nodes.     

一种新型的抗辐射加固锁存器

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

High performance energy efficient radiation hardened latch for low voltage applications

Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits show a lesser immunity against soft error, because of the smaller device node capacitances in nanoscale technologies and near-threshold voltage operation. Due to these reasons, the tolerance of the sequential circuits to SEUs is an important consideration in nanoscale near threshold CMOS design. This paper presents an energy efficient SEU tolerant latch. The proposed latch improves the SEU tolerance by using a clocked Muller- C and memory elements based restorer circuit. The parasitic extracted simulations using STMicroelectronics 65 nm CMOS technology show that by employing the proposed latch, an average improvement of ∼40% in energy delay product (EDP), is obtained over the recently reported latch. Moreover, the proposed latch is also validated in a TCAD calibrated PTM 32 nm framework and PTM 22 nm CMOS technology nodes. In 32 nm and 22 nm technologies, the proposed latch improves the EDP ∼12% and 59% over existing latches respectively.     

10～20MeV中子引起单粒子翻转的微分析

我们用Monte Carlo方法模拟了10～20MeV中子引起的单粒子翻转。计算了引起电离能量沉积的五种概率。对于一个临界电荷分别为0．05、0．10和0．15pC的16K静态RAM存储器硅片,我们计算了引起单粒子翻转的入射中子平均注量及由(n,α)反应引起的单粒子翻转的概率。给出了三次接近入射中子平均注量的中子引起的单粒子翻转中,在灵敏单元内与电离能量沉积相关的一系列物理量的计算结果。这些结果能够为10～20MeV中子引起的单粒子翻转提供统计的和微观描述的信息。     

基于C单元反馈回路的容SEU锁存器设计

随着电子技术的不断发展,集成电路的特征尺寸不断缩小,导致电路对宇宙高能粒子引发的单粒子翻转愈发敏感。提出了一种对单粒子翻转完全免疫的抗辐射加固锁存器。该锁存器利用具有过滤功能的C单元构建反馈回路,并在锁存器末端使用钟控C单元来阻塞传播至输出端的软错误。HSPICE仿真结果显示,在与TMR锁存器同等可靠性的情况下,该锁存器面积下降50%,延迟下降92%,功耗下降47%,功耗延迟积下降96%。