一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种新的相位开关实现技术及其在射频双模预分频器中的应用

提出了一种新的相位开关实现技术.基于这种技术设计了一个2/3分频器单元,该单元结构简单,工作频率高,功耗低.为了验证该技术,采用0.25μm CMOS数字工艺实现了一个128/129双模预分频器.对该芯片的测试结果表明其能正确工作于GHz频率范围.当工作频率为2.3GHz时,它消耗的电流仅为13.5mA(2.5V电源电压),芯片面积为0.47mm×0.47mm.     

5 GHz 0.18-μm CMOS 可编程分频器

提出了一种2.4GHz ZigBee 应用的可编程分频器,其分频模值在2403-2480之间变化。该分频器基于双模分频器和吞咽计数器架构,功耗和面积得到了有效降低。芯片采用0.18-μm CMOS混合信号工艺实现,当输入信号达到7.5dBm时,分频器可正常工作的频率范围覆盖1-7.4 GHz,在100KHz频偏处的输出相位噪声为-125.3dBc/Hz。分频器核心电路消耗电流4.3mA（1.8V电源电压）,核心面积0.015mm2。测试结果表明该可编程分频器能很好的应用在所需的频率综合器中.     

一种新的相位开关实现技术及其在射频双模预分频器中的应用

提出了一种新的相位开关实现技术 .基于这种技术设计了一个 2 / 3分频器单元 ,该单元结构简单 ,工作频率高 ,功耗低 .为了验证该技术 ,采用 0 .2 5μm CMOS数字工艺实现了一个 12 8/ 12 9双模预分频器 .对该芯片的测试结果表明其能正确工作于 GHz频率范围 .当工作频率为 2 .3GHz时 ,它消耗的电流仅为 13.5 m A(2 .5 V电源电压 ) ,芯片面积为 0 .4 7mm× 0 .4 7m m.     

一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器,集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时,在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时,不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。     

带高速电流舵DAC的直接数字频率合成器

本文给出了一种高速SiGe BiCMOS直接数字频率合成器设计。该数字频率合成器单片集成了高速DDS数字核,10位差分电流舵 DAC,串/并接口和时钟控制逻辑。芯片采用0.35μm SiGe BiCMOS标准工艺流片,工作在1GHz系统频率。测试结果显示,该DDS能够生成高达400+ MHz的捷变模拟sine波形。     

基于0.6μm BCD工艺的迟滞电流模LED驱动芯片设计*

基于0.6μm BCD工艺设计了一种高转换效率的迟滞电流模控制的白光LED驱动芯片。该驱动器可工作在6~40V电源电压下,其最大输出驱动电流可达1.0A,最大开关频率可达1MHz,输出电流误差小于?5%,转换效率大于80%。文章重点介绍了芯片内部影响输出电流精度的高侧电流检测电路以及高速比较器的设计,并给出了所设计的迟滞电流模白光LED驱动器的相关仿真和测试结果。     

基于InP DHBT工艺的6 bit DAC设计与实现

基于InP双异质结双极晶体管(DHBT)工艺设计并实现了一款6 bit高速数模转换器(DAC)芯片,该InP工艺DHBT器件的电流增益截止频率大于200 GHz,最高振荡频率大于285 GHz.DAC芯片采用R-2R梯形电阻电流舵结构,输入级采用缓冲预放大器结构,实现输入缓冲及足够高的增益;D触发器单元采用采样/保持两级锁存拓扑结构实现接收数据的时钟同步;采用开关电流源单元及R-2R电阻单元,减小芯片体积,实现高速采样.该DAC最终尺寸为4.5 mmX3.5 mm,功耗为3.5W.实测结果表明,该DAC可以很好地实现10 GHz采样时钟下的斜坡输出,微分非线性为+0.4/-0.24 LSB,积分非线性为+0.61/-0.64 LSB.     

基于90 nm CMOS工艺的37 GHz分频器

对高速分频器的注入锁定特性进行了研究,并实现了一个基于电流模逻辑的分频器。该分频器采用了电感峰值技术,分频范围可达25~37.3 GHz,电源电压为1.2 V,功耗为24 mW。芯片采用TSMC 90 nm CMOS工艺设计制造,并给出了测试结果。     

Design of 20-44 GHz broadband doubler MMIC

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at VDD = 3.5 V, VSS = -3.5 V, Id = 200 mA and the chip size is 1.5 ×1.8 mm2.     

An S‐Band Multifunction Chip with a Simple Interface for Active Phased Array Base Station Antennas

An S‐band multifunction chip with a simple interface for an active phased array base station antenna for next‐generation mobile communications is designed and fabricated using commercial 0.5‐μm GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial‐to‐parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6‐bit phase shifting and 6‐bit attenuation, it provides a wideband performance employing a shunt‐feedback technique for amplifiers. With a compact size of 16 mm² (4 mm × 4 mm), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.     

Compact InP-based HBT VCOs with a wide tuning range at W- andD-band

Compact monolithic integrated differential voltage-controlled oscillators (VCOs) operating in W-band were realized using InP-based heterojunction bipolar transistors (HBTs). The oscillators, with a total chip size of 0.6 by 0.35 mm², are based on a balanced Colpitts-type topology with a coplanar transmission-line resonator. By varying the voltage across the base-collector junction of the HBT in the current mirror and by changing the current in the VCO, the oscillation frequency can be tuned between 84 and 106 GHz. At 100 GHz, a differential voltage swing of 400 mV is obtained, which should be sufficient to drive 100 Gb/s digital logic. By combining the balanced outputs of a similar differential VCO in a push-push configuration, a compact source with close to -10 dBm output power and a tuning range between 138 and 150 GHz is obtained     

基于InP HBT工艺的高功率高谐波抑制W波段宽带八倍频器MMIC

基于0.7μm InP HBT工艺,设计实现了一种高功率高谐波抑制比的W波段倍频器MMIC。电路二倍频单元采用有源推推结构,通过3个二倍频器单元级联形成八倍频链,并在链路的输出端加入输出缓冲放大器,进一步提高倍频输出功率。常温25℃状态下,当输入信号功率为0 dBm时,倍频器MMIC在78.4~96.0 GHz输出频率范围内,输出功率大于10 dBm,谐波抑制度大于50 dBc。芯片面积仅为2.22 mm²,采用单电源+5 V供电。     

A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider

We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f/sub T//2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.     

A Miniaturized Monolithic 18–40 GHz Sub-harmonic Mixer

In this paper, a miniaturized 18–40 GHz sub-harmonic mixer is designed and implemented with 0.15 μm GaAs pHEMT process. The proposed mixer employs anti-parallel diode pair with parallel to ground configuration, and a novel coupler structure to feed RF and LO signals, resulting in broadband performance and compact chip size. The measured conversion loss is 10.3–13.5 dB in a wide operation frequency band of 18–40 GHz. The chip size is 0.66 mm².     

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS

This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm~2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.     

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm². Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.     

A 40 GHz Differential Push-Push VCO in 0.18 $mu{rm m}$ CMOS for Serial Communication

A 40 GHz differential CMOS push-push VCO is proposed for high-frequency applications. It is shown analytically that the phase noise of the VCO output at the full-rate frequency is close to 6 dB higher than that of the half-rate frequency. The result of the phase noise analysis is verified by simulations and measurements. A phase noise of $-$ 101 dBc/Hz was achieved at 1 MHz offset frequency. The proposed push-push VCO design enables higher VCO frequency operation with differential output, which is suitable for millimeter wave frequency synthesizers.