A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions

Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel workfunctions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge. Buried channel, gate workfunction, metal gate, SiGe-channel confinement effects, SiGe-channel MOSFET, silicon germanium, ultrathin-body (UTB).     

An analytical back gate bias dependent threshold voltage model forSiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide     

Circuit level prediction of device performance degradation due to negative bias temperature stress

A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I–V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

Effect of trench edge on pMOSFET reliability

Scaling of MOSFET increases the portion of the device channel that is affected by proximity to the shallow trench isolation (STI) trench. Experimental data show that this proximity effect results in a channel-width dependent hot-carrier degradation of pMOSFETs in a 0.25 μm CMOS technology. Device simulations are used to show that electric field differences between the STI edge and center channel region are responsible for the channel-width dependent degradation. Discrete device measurements and product burn-in data are presented to support this explanation of the pMOSFET degradation mechanism.     

Hot-carrier degradation analysis based on ring oscillators

This paper presents a new test circuit for hot-carrier degradation analysis based on a ring oscillator. The devices and the test circuit were fabricated using Philips’ 0.35 μm CMOS technology. For single device, AC and DC hot-carrier-induced degradation are the same if the effective stress time is carefully taken into account. For circuit level degradation, the frequency of the ring oscillator, on logarithmic scale degrades at the same slope as the saturation drain current of nMOS transistor degrades, while pMOS transistor degradation is much smaller than nMOSFET degradation and can be ignored. For universal applications, the circuit degradation can be expressed by MOSFETs I_dsat degradation with NSF (nMOSFET degradation speed factor) and PSF (pMOSFET degradation speed factor). Formulae for NSF and PSF calculations are derived. Simulations with Philips PSTAR circuit simulator were also performed, which well agree with the experiment results.     

Low frequency noise in SiGe-base heterojunction bipolar transistors and SiGe-channel metal oxide semiconductor field effect transistors

We show that low frequency noise (LFN) in SiGe-base heterojunction bipolar transistors and SiGe-channel pMOSFETs may be made significantly lower than that in their all-Si counterparts and indicate how this can be done. Optimization of LFN in SiGe channel pMOSFETs follows from a calculation involving a novel analytical model, which accounts for both static and LFN characteristics of SiGe-channel devices.     

薄膜积累型SOI pMOSFET

对薄膜积累型SOI pMOSFET的制备和特性进行了研究.把一些特性和反掺杂型SOI pMOSFET进行了比较.其亚阈值斜率只有69mV/decade,而且几乎没有DIBL效应.漏击穿电压为10.5V,与反掺杂型相比,提高了40%.饱和电流为130μA/μm,比反掺杂型提高了27%以上.在3V工作电压下,101级SOI CMOS环形振荡器的单级门延迟为56ps.     

Activation level in boron-doped thin germanium-on-insulator (GeOI): Extraction method and impact of mobility

We hereby present a non-destructive method for extracting the activation level on boron-doped germanium-on-insulator (GeOI) wafers, with a discussion on the impact of the hole mobility model. This method combines Monte Carlo boron profile simulations with optical Ge layer thickness T_Ge and electrical sheet resistance R_sh measurements. As B atoms are known not to diffuse in Ge for the usual activation temperatures (<800 °C), we can assume that the as-implanted dopant profile remains unchanged after annealing (no modelling of boron diffusion required). We highlight that the knowledge of the hole mobility dependence on activated impurities concentration in Ge is of paramount importance. Several experimental and theoretical models are available in the literature. After relative validity assessments, all of them have been implemented for extraction and unfortunately yield different values scattered over nearly one decade. Still, the lower-bound concentration 2.7×10¹⁹ cm⁻³ is in the range of the state-of-the-art values for B-implanted crystalline Ge and has proven suitable for functional GeOI pMOSFET demonstration.     

A physical-based pMOSFETs threshold voltage model including the STI stress effect

The physical threshold voltage model of pMOSFETs under shallow trench isolation(STI) stress has been developed.The model is verified by 130 nm technology layout dependent measurement data.The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET.The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11%improvement of average delay time.This indicates the importance of STI stress consideration in circuit design.     

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V/sub DS/), counter doping layer thickness (x/sub CD/), counter doping concentration (N/sub CD/), substrate doping concentration (N/sub sub/) and source/drain junction depth (x/sub j/), and the new model performs satisfactorily in the sub-0.1 /spl mu/m regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.     

STI应力效应下的pMOSFET阈值电压物理模型

本文提出了浅沟道隔离（STI）应力效应下的P型MOSFET的阈值电压物理模型,并用不同STI版图位置的130纳米的器件数据进行了验证。基于此STI阈值电压模型,我们对比了p型MOSFET和n型MOSFET在STI应力下的阈值电压和迁移率的变化。数据表明,相比n型MOSFET,p型MOSFET的阈值电压更少地受到STI应力影响,但迁移率却更多地受到STI应力影响。基于此STI阈值电压模型,我们进行了九级震荡环电路的模拟。模拟数据显示,适当的STI应力能使电路平均延迟时间提高约11%,同时也说明了STI应力模型在电路设计中的重要性。     

DC and RF Characteristics of Si0.8Ge0.2 pMOSFETs: Enhanced Operation Speed and Low 1/f Noise

This paper reports on our investigation of DC and RF characteristics of p‐channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained Si_0.8Ge_0.2 channel. Because of enhanced hole mobility in the Si_0.8Ge_0.2 buried layer, the Si_0.8Ge_0.2 pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the Si_0.8Ge_0.2 pMOSFET was much lower than that in the all‐Si counterpart, regardless of gate‐oxide degradation by electrical stress. These results suggest that the Si_0.8Ge_0.2 pMOSFET is suitable for RF applications that require high speed and low 1/f noise.     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.     

Experimental 0.1 μm p-channel MOSFET withp+-polysilicon gate on 35 Å gate oxide

Very-high-transconductance 0.1 μm surface-channel pMOSFET devices are fabricated with p⁺-poly gate on 35 Å-thick gate oxide. A 600 Å-deep p⁺ source-drain extension is used with self-aligned TiSi₂ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices     

SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。