Hysteresis behavior in 85-nm channel length vertical n-MOSFETsgrown by MBE

Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V_DS>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode     

Dynamic current-voltage characteristics of III-N HFETs

A comparative study of the dynamic current-voltage (DI-V) characteristics of III-N heterojunction and double heterojunction field-effect transistors (HFETs and DHFETs) reveals that the current and RF power collapse in HFETs arise from modulation of device series resistances under large input signal. A model based on space-charge limited current through the depletion regions formed at the gate edges due to the charge trapping explains the DI-V behavior and other observations related to the RF current collapse in III-N HFETs.     

Pseudo-MOSFET Substrate Effects of Drain Current Hysteresis and Transient Behavior

A large drain current-gate voltage hysteresis of evaporated metal contact pseudo-MOSFETs ( $Psi$-MOSFET) is reported. The $Psi$-MOSFET drain current exhibits a hysteresis when the gate voltage is swept from negative to positive and from positive to negative voltages. Optical illumination, elevated temperatures, and decreased sweep rate during the measurements eliminate this phenomenon. The reason for this behavior is related to electron–hole pair generation in the substrate. In this paper, we report systematic studies and device simulations to document and understand these substrate effects during $Psi$ -MOSFET measurements.      

Gate pulse electrical method to characterize hysteresis phenomena in organic field effect transistor

Hysteresis phenomena in the current–voltage characteristics of organic thin-film transistors (OTFTs) between the up and down sweeps are commonly observed. This hysteresis behavior is strongly affected by the trapping-effect. In this work, we present a new experimental technique to study these phenomena. The technique is based on the time-dependent drain current measurements as a function of a pulsed gate voltage. The decay of the drain current observed when a gate bias is applied to the gate electrode is correlated to the trapping-detrapping effects in the silicon oxide and/or at the organic semiconductor/silicon oxide interface. We show how to use this pulse gate electrical method to characterize the true device performances (threshold voltage, carrier mobility) of petacene organic field effect transistors (OFETs) with SiO₂ gate dielectric under different pulsed conditions, avoiding the pitfalls due to the presence of the hysteresis effect when using classical static data analysis methods. Moreover, we demonstrate that the charge carrier mobility is less affected by the trapping and detrapping phenomena than the threshold voltage.     

Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10^-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO2energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.     

Latch and hot-electron gate current in accumulation-mode SOIp-MOSFET's

Simultaneous measurements of drain and gate currents in short-channel accumulation-mode SOI p-MOSFET'MOs demonstrate that a latch mechanism may occur in these devices and induce an anomalous behavior of the hot-electron gate current: distortion of I_g(V _g) curves, hysteresis and excessively high gate current values. 2-D MEDICI simulations based on the lucky-electron model qualitatively reproduce the measurements in the latch regime, and explain the unusual gate current dependence on drain and gate biases. The results are of relevance for reliability and modeling issues     

Tetrahedral-shaped recess (111)A facet channel AlGaAs/InGaAsheterojunction field-effect transistor with an InGaAs floating quantumdot gate

A transistor and memory operation of a new AlGaAs/InGaAs heterojunction field-effect transistor (HFET) in a tetrahedral-shaped recess (TSR) on the (111)B GaAs substrate was investigated at a temperature up to 120 K. The TSR-FET memory has a channel on the (111)A side surfaces of the recess and a single floating quantum dot (QD) gate at the bottom. Owing to the particular shape of the TSR structure, the charge in the floating QD gate can effectively modulate the channel current. We found a clear hysteresis in the current-voltage (I-V) characteristics with an abrupt increase and decrease in the current at the subthreshold gate bias region. Random telegraph signals with a constant amplitude of about 70 nA were also observed in the memory retention characteristics. These phenomena were considered to be attributed to the current modulation by hole charging/discharging in the QD     

Inclusion of impact ionization in the backgating of GaAs FETs

It is shown that the familiar threshold behavior of the backgate current of GaAs MESFETs has hysteresis. This is associated with an S-type negative differential conductivity (S-NDC) of the semi-insulating substrate. It is difficult to account for this hysteresis using conventional trap-fill-limited (TFL) theory, and it is attributed to the impact ionization of traps in the substrate. A simple model of this ionization, involving two trap levels, is used to incorporate its effect into an existing analytical model of GaAs FETs. The result is a qualitative interpretation of the backgating characteristics of GaAs MESFETs. The calculations show that a simple combination of two ohmic elements to represent parasitic resistances, and a nonohmic one to represent impact ionization in the substrate, can imitate the observed backgating behavior     

Dependence of Fermi level positions at gate and substrate on thereliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υ_g^-). The oxide breakdown strength (Q_bd) is less for p⁺ poly-Si gate than for n⁺ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P⁺ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide     

Optoelectronic integration of a GaAs/AlGaAs bistable field effecttransistor (BISFET) and LED

The bistable field effect transistor (BISFET) is a novel inversion-channel switching device exhibiting abrupt current transitions and hysteresis in its output characteristics. The semiconductor structure of the BISFET is compatible with a range of electronic and optoelectronic devices. In this work, integration of a BISFET with an LED is reported. Both devices have been implemented on a single semiconductor substrate using a single fabrication sequence. The BISFET is used to current drive the LED. Abrupt transitions and hysteresis are seen in the optical output from the circuit in the range of gate voltage from 1.75 V to 1.9 V     

High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

This paper examined the feasibility of applying a highly sensitive metal-oxide-semiconductor (MOS) tunneling temperature sensor, which was compatible with current CMOS technology. As the sensor was biased positively at a constant voltage, the gate current increased more than 500 times when the sensor was heated from 20/spl deg/C to 110/spl deg/C. However, when the sensor was biased at a constant-current situation, its gate voltage magnitude changed significantly with substrate temperature, with a sensitivity exceeding -2 V//spl deg/C. The improvement of temperature sensitivity in this paper is one thousand times over the sensitivity of a conventional p-n junction, i.e., namely, about -2 mV//spl deg/C. Regarding a temperature sensor array, this paper proposes a method using gate current gain, rather than absolute gate current, to eliminate the gate current discrepancy among sensors. For constant current operation, a sensitivity exceeding 10 V//spl deg/C can be obtained if the current level is suitable. Finally, this paper demonstrates a real temperature distribution for on-chip detection. With such a high temperature-sensitive sensor, accurate temperature detection can be incorporated into common CMOS circuits.     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Numerical simulation of avalanche hot-carrier injection in short-channel MOSFET's

Based on two-dimensional MOSFET simulation, the substrate and gate currents resulting from impact ionization generated electron-hole pairs and their injection into the gate oxide are calculated. The improved injection model uses a nonMaxwellian distribution function and considers separate contributions to the gate current from both thermionic-emission and oxide-barrier tunneling. A fine structure in experimentally observed I/sub g//sup e/ vs. v/sub g/ curves for thin-oxide devices at v/sub g/ approximately=2.3v/sub d/ is simulated. Simulation of a lightly doped drain (LDD) MOSFET also reveals the unusual feature of a double hump in the substrate current and an abrupt increase of the gate current beginning at v/sub g/ approximately=3/2v/sub d/.<>     

A thorough study of quasi-breakdown phenomenon of thin gate oxidein dual-gate CMOSFET's

The conduction mechanism of the quasibreakdown (QB) mode for thin gate oxide has been studied in a dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide quasibreakdown (QB). Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si-SiO₂ interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Twelve V_g, I_sub, I_sd/ versus time curves and forty eight I-V curves of carrier separation measurements have been demonstrated. All the curves can be explained in a unified way by the LPDR QB model and the proper interpretation of the carrier separation measurements. Particularly, under substrate injection stress condition, there is several orders of magnitude increase of I_sub(I_sd/) at the onset point of QB for n(p)-MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate, consequently, cold holes are left in the substrate and measured as substrate current. These cold holes have no contribution to the oxide breakdown and thus the lifetime of oxide after QB is very long. Under the gate injection stress condition, there is sudden drop and even change of sign of I_sub(I_sd/) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate     

Oxide current in MOS transistors operated under charge pumping conditions

The present paper describes an alternative approach for isolating the oxide current from the gate current (GC) and its use for characterizing the bulk oxide in MOS transistors. The method is based on measurements of the gate as well as the substrate currents of MOS transistors pulsed by a train of square wave pulses under charge pumping conditions.The measurements are done on various experimental devices and different gate and drain/source voltage biasing. The GC has been measured and was found to be of typical behavior when it is plotted with respect to the gate voltage. Moreover, the gate and substrate currents are found to be of complementary shapes when plotted with respect to gate voltage. This behavior is made useful in studying and characterizing the oxide and the interface of MOS transistors.     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude     

Effect of back-gate bias on tunneling leakage in a gated P+-n diode

The author describes observations of a thin-oxide gate-controlled p⁺-n diode in which tunneling leakage current characteristics were seen to have both dependent and independent components due to the substrate bias voltage. Previously proposed models for leakage current do not account for this observation. It is argued that this observation can be reasonably explained by the nature of the modulation of the surface space-charge region over the heavily doped p⁺ region as well as over the n-type substrate     

On the temperature dependence of subthreshold currents in MOS electron inversion layers

It has been observed that the “n” factor which enters into the exponential dependence of drain current on gate voltage for MOS transistors operating in the weak inversion region, exhibits a significant temperature dependence. This effect is correlated with the increase of interface state density towards the band edges and the variation of the space-charge capacitance.     

Deep cryogenic noise and electrical characterization of thecomplementary heterojunction field-effect transistor (CHFET)

This paper discusses a characterization at 4 K of the complementary heterojunction field-effect transistor (CHFET), to examine its suitability for deep cryogenic (<10 K) readout electronics applications. The CHFET is a GaAs-based transistor analogous in structure and operation to silicon CMOS. The electrical properties including the gate leakage current, subthreshold transconductance, and input-referred noise voltage were examined. It is shown that both n-channel and p-channel CHFET's are fully functional at 4 K, with no anomalous behavior, such as hysteresis or kinks. Complementary circuit designs are possible, and a simple CHFET-based multiplexed op-amp is presented and characterized at 4 K. The noise and gate leakage current of the CHFET are presently several orders of magnitude too large for readout applications, however. The input-referred noise is on the order of 1 μV/√(Hz) at 100 Hz for a 50×50 μm n-channel CHFET. The gate current is strongly dependent on the doping at the gate edge, and is on the order of 10^-14 A for a 10×10 μm ² n-channel CHFET with light gate-edge region doping     

Freeze-out effects on NMOS transistor characteristics at 4.2 K

Detailed substrate current characteristics of nMOSTs at 4.2 K were obtained with a view to elucidating their transient (hysteresis) and kink behavior below carrier freeze-out. A great similarity with room-temperature behavior is found, indicating that analogous expressions for the substrate current I_B can be used to calculate the transient time constant that follows from the forced depletion layer formation (FDLF) model reported previously by the authors (see ibid., vol.ED-35, p.1120-5, 1988). In a second part to this work, it will be demonstrated that both the substrate and the cooling bias have a marked influence on the kink. These effects can be fully understood with the FDLF model