Correlation between predicted cause of SRAM failures and in-line defect data

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.     

Voltage Contrast for Gate-Leak Failures Detected by Electron Beam Inspection

We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time.     

A Comprehensive Study of Cobalt Salicide-Induced SRAM Leakage for 90-nm CMOS Technology

Cobalt salicide-induced static random access memory (SRAM) leakage in 90-nm technology is investigated in this paper. We found that the junction leakages are the origins of abnormal SRAM leakage, leading to a high direct-drain quiescent current and low function yield at wafer level. Cobalt salicide penetration at active edges is a dominant path for the junction leakage current. Both junction-area-intensive and active-edge-intensive test structures are employed to characterize the junction leakage. The SRAM function failure sites are carefully examined using conducting atomic force microscope and transmission electron microscope techniques. A full-factorial design of experiment (DOE) is implemented to systematically study the influences of Co thickness and temperatures of RTP1 and RTP2 on the junction leakage characteristics. Within the DOE window, it is found that both junction area and junction edge leakages increase with the Co thickness. The RTP1 temperature is critical in controlling Co salicide penetration at the active edge, while the RTP2 temperature is the main factor that affects the junction area leakage. SRAM leakage can be minimized by optimizing the salicide process scheme.     

SRAM版图布局方向对产品失效率的影响

静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。     

源端射频干扰下SRAM的抗扰性分析

目前已有一些在ESD和电磁干扰下存储器行为的表征研究,但对静态随机存取存储器(SRAM)的连续波抗扰度的频率响应特性的研究很少.文章研究了 SRAM在射频电磁干扰下的失效行为与机理.对SRAM芯片进行射频干扰测试发现,SRAM失效行为与其工作模式相关.使用Hspice进行晶体管级仿真.结果表明,SRAM处于数据保持时,...     

Failure analysis of 6T SRAM on low-voltage and high-frequency operation

Careful analysis of SRAM bit failure at high-frequency operation has been described. Using the nanoprober technique, MOS characteristics of failure bit in actual memory cells had been measured directly. It was confirmed that the drain current of a PMOS was about one order in magnitude smaller and the threshold voltage was about 1 V higher than that for normal bits. A newly developed, unique selective etching technique using hydrazine mixture showed these degradations were caused by local gate depletion, and TEM observation showed the PMOS gate poly-Si of the failure bit had a huge grain. Minimizing grain size of the gate poly-Si is found to be quite effective for improving drain current degradation and suppressing this failure mode.     

28 nm低功耗工艺SRAM失效分析

在28 nm低功耗工艺平台开发过程中,对1.26 V测试条件下出现的SRAM双比特失效问题进行了电性能失效模式分析及物性平面和物性断面分析.指出失效比特右侧位线接触孔底部空洞为SRAM制程上的缺陷所导致.并通过元素成分分析确定接触孔底部钨(W)的缺失,接触孔底部外围粘结阻挡层的氮化钛(TiN)填充完整.结合SRAM写操作的原理从电阻分压的机理上解释了较高压下双比特失效,1.05 V常压下单比特不稳定失效,0.84 V低电压下失效比特却通过测试的原因.1.26 V电压下容易发生的双比特失效是一种很特殊的SRAM失效,其分析过程及结论在集成电路制造行业尤其是对先进工艺制程研发过程具有较好的参考价值.     

基于March C-算法的SRAM芯片的SEU失效测试系统

本文为实现SRAM芯片的单粒子翻转故障检测,基于LabVIEW和FPGA设计了一套存储器测试系统：故障监测端基于LabVIEW开发了可视化的测试平台,执行数据的采集、存储及结果分析任务;板卡测试端通过FPGA向参考SRAM和待测SRAM注入基于March C-算法的测试向量,通过NI公司的HSDIO-6548板卡采集两个SRAM的数据,根据其比较结果判定SEU故障是否发生。该系统可以实时监测故障状态及测试进程,并且具有较好的可扩展性。     

Mechanism and detection of poly gate leakage with nonvisual defects by voltage contrast inspection

The research aims at nonvisual defects causing the poly gate leakage failure and the corresponding inline voltage-contrast (VC) inspection. Electron beam inspection (EBI) begins to be frequently used for scanning either SRAM or DRAM cell area in nano-scaled technologies. The research, furthermore, extends EBI to logical area of an ASIC product and proposes an inline detectable methodology for gate leakages. Extreme tiny and nonvisual residues could happen during gate etch processes by the step height between active area (AA) and shallow trench isolation (STI), and the tiny defects are difficult to be located even some of those did lead to chip probe (CP) test failure. The subsequent implant processes would punch through those tiny poly residues, make the residue being conductive, and finally electrons on the gate would leak to the ground through the residue. Those nonvisual residues act as bridges for gate leakages. EBI with designed positive charging modes was applied into the series of implement steps and found the leakage by a significant voltage contrast signal post the source/drain implantation. The bright VC of the gate poly implied the leakage electrons charging on the gate. A series of process experiments based on the model for reducing leakages was tested and quickly verified by the EBI in front end of the line. An optimal process integration condition was soon carried out with a significant chip yield enhancement.     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

Manufacturing enhancements for CoSi/sub 2/ self-aligned silicide at the 0.12-/spl mu/m CMOS technology node

As integrated circuit manufacturing moves to the 0.12-/spl mu/m and finer-line technologies, a more comprehensive understanding of the manufacturability of the cobalt silicide (CoSi/sub 2/) module is needed. In this paper, a detailed study of the manufacturability of cobalt self-aligned silicide (Salicide) for the 0.12-/spl mu/m and finer technology nodes is discussed. Experimental design for the CoSi/sub 2/ processing steps included cobalt (Co), titanium (Ti), and titanium nitride (TiN) depositions; the first and second rapid thermal anneals (RTA1 and RTA2) and the selective metal etch. Grain structure (by X-ray diffraction), surface roughness (by atomic force microscopy), sheet resistance, thickness uniformity and leakage current measurements were taken to characterize the SAlicide process module. The results show that by using a TiN rather than Ti capping layer: a) the CoSi/sub 2/ sheet resistance nonuniformity has been improved; b) the CoSi/sub 2/ thickness is independent of the capping layer thickness; and c) CoSi/sub 2/ to silicon interface roughness is reduced, thus reducing junction leakage currents. Anneal studies indicate the RTA1 temperature dominates the CoSi/sub 2/ grain structure and grain size with higher annealing temperatures resulting in rougher CoSi/sub 2/ surfaces and higher junction leakage currents.     

Embed SRAM IDDOFF fail root cause identification by combination of device analysis and localized circuit analysis

SRAM is most important component in the logic product. The failure analysis on the SRAM is well developed, but the SRAM IDDOFF analysis is still challenging for the FA engineers. The product has passed the functional test when IDDOFF is measured. This will make electrical fault isolation very difficult. It will be easy to verify the IDDOFF leakage at die level, but difficult or impossible to verify the leakage at the transistor level. In this paper, a SRAM IDDOFF failed unit was analyzed and the conventional EMMI method was employed to do the fault isolation. The hotspot was easily found in the SRAM area. The EMMI signal cover the entire SRAM block, which indicates a gross leakage in the SRAM block. Subsequent layer by layer analysis didn't find any abnormality until contact level. Nanoprobing at contact level also shows nothing abnormal. To understand the leakage path, the SRAM circuit was studied under DC bias condition and combined with a cross-section analysis of the structure. Thus, a suspected leakage path was proposed. Based on this suspect the leakage can only be simulated at M1 level, and then the experiment was redesigned at Via1 level. The leakage was successfully verified by the nanoprobing DC measurement at M1 level. Finally, the TEM analysis confirms the root cause for the IDDOFF fail.     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

A novel nine transistor (9T) CMOS SRAM cell design at 32 nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution at array-level, a novel write bitline balancing technique is proposed to reduce the leakage current. By optimizing its size and employing the proposed write circuit technique, 33% power dissipation saving is achieved in memory array operation compared with the conventional 6T SRAM based design. A new metric that comprehensively captures all of these figures of merit (and denoted to as SPR) is also proposed; under this metric, the proposed 9T SRAM cell is shown to be superior to all other cell configurations found in the technical literatures. The impact of the process variations on the cell design is investigated in detail. HSPICE simulation shows that the 9T SRAM cell demonstrates an excellent tolerance to process variations comparing with the conventional SRAM cells.     

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)) weaken MOSFETs with time. The impact of such device degradation can be severe in Static Random Access Memories (SRAMs) wherein stability is governed by relative strengths of FETs. Degradation in stability with time under ‘worst case condition’ gets more important because of reduced guard-banding due to process induced instability. In this work, circuit insights into worst-case conditions and effect of NBTI and PBTI, individually and in combination, on the stability of an SRAM cell are presented. It is shown that measurable quantities such as static noise-margin are not sufficient to completely understand the combined effect of NBTI and PBTI. Monte-Carlo simulations are performed in a 45 nm PDSOI technology to estimate the increase in cell failure probability with time. In worst case, NBTI and PBTI both degrade read stability (significantly) and writability (marginally). Further, we analyze the choice of optimal power supply considering the trade-off between short-term stability (due to process variations) and long-term stability (due to NBTI/PBTI) to achieve six-sigma confidence in SRAM cell robustness.     

Improved SRAM failure diagnosis for process monitoring via current signature analysis

SRAM's are frequently used as monitor circuits for defect related yield, due to the ease of testing and the good correlation to the yield characteristics of logic circuitry. For the identification of the failure/fault type and the nature of the defect causing the failure, measured failbitmaps are mapped onto a failbitmap catalog obtained from defect-fault simulation. Often this mapping is not unique. A given failbitmap can be caused by several faults or defects.In this contribution, the application of current signature analysis is demonstrated for a stand-alone 16kx1 SRAM monitor circuit. It is found that the resolution of the failbitmap-fault-defect catalog can be improved considerably by additional current signature measurements. The interpretation of current measurements is based on simulation of the possible faults contained in the failbitmap catalog under the operating conditions in the current test. There was good agreement between the simulated and measured current values.With the aid of current measurements, more yield learning information is obtained from the process monitoring vehicle. In some cases, the shorted nodes inside a SRAM cell can be determined exactly. This eases the localization of the failure and is of practical importance for the sample preparation in physical failure analysis.     

Standby supply voltage minimization for deep sub-micron SRAM

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V_DD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when V_DD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby V_DD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.     

驱动能力对SOI SRAM单元单粒子效应的影响仿真

采用silvaco软件对抗辐射不同沟道宽度的PD SOI NMOS器件单元进行了三维SEU仿真,将瞬态电流代入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟。通过这种电路模拟的方法,可以得到SRAM存储单元的LET阈值。通过对比LET阈值的实际测量值,验证了这种方法的实用性,并对不同驱动能力的SRAM单元进行了翻转效应的对比。在NMOS和PMOS驱动比相同的情况下,沟道宽度越大,SRAM的翻转LET阈值反而越高。     

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.     

Principles of an analytical method of optimization of structure parameters of avalanche heterophotodiodes with separated regions of absorption and multiplication

Principles of an analytical system of physical design of avalanche heterophotodiodes with separate regions of absorption and multiplication (AHPD with SRAM) are presented. The system is based on analytical expressions for the field of the avalanche breakdown of the p–n heterostructure and the interband tunnel current in it. This current determines the minimum noise level in the AHPD with SRAM based on direct band semiconductors. The considered method strongly facilitates optimization of the doping levels of the heterostructure layers and their thicknesses. In addition, it gives significantly more pronounced physical content to the optimization process.