一种基于优先级表的实时调度方法

针对单处理器实时系统动态调度问题进行了研究,分析任务的到达时间、执行时间、截止时间和空闲时间等任务属性的敏感度和影响度,提出了一种基于优先级表的调度算法PTBM,使相对截止期越小、空闲时间越大的任务优先级越高。对关于实时任务属性敏感度和影响度的结论验证和与传统的EDF、LLF和PTD算法的对比进行仿真实验,仿真结果表明基于优先级表设计的实时调度算法PTBM具有较高的调度成功率。该方法可应用于实时系统的实时任务的动态调度中。     

异构系统中的综合性启发式任务调度算法

任务的单个属性常作为基于优先驱动的表调度算法的优先级,针对这种方法常出现优先级相同的情况,提出一个综合性启发式算法HCPFS。算法分三个优先级选择任务进行调度,从高到低依次为：关键路径上的任务、就绪任务到出口任务的路径长度和后继任务数。调度过程中,算法采用任务复制和空闲时间区段任务插入的方法。采用随机生成图法和任务图集进行了算法模拟和比较,实验数据表明HCPFS算法具有更好的调度性能。     

一种面向动态部分可重构片上系统的列表式软硬件划分算法

并行计算是提高系统资源利用率的重要手段,越来越多的多处理器片上系统通过集成具有不同功能特点的处理器来满足不同计算任务的需求.具备动态部分可重构特性的异构多处理器片上系统(Dynamic Partial Reconfiguration-Heteroge-neous Multiprocessor Systems-on-Chip,DPR-HMPSoC)因其并行性好、计算效率高而被广泛使用,而低复杂度和高求解性能的软硬件划分算法是充分发挥其计算性能优势的重要保证.已有的相关软硬件划分算法时间复杂度高,且对DPR-HMPSoC平台的支撑不足.针对上述问题,首先提出了一种列表启发式软硬件划分与调度算法,其通过构建基于任务优先级的调度列表,完成任务的调度、映射、FPGA动态部分可重构区域划分等一系列操作;接着给出了软件应用建模、计算平台建模及所提算法的详细设计方案.仿真实验结果表明,所提算法与混合整数线性规划(Mixed Integral Linear Programming,MILP)和蚁群优化(Ant Colony Optimization,ACO)算法相比,可有效减少求解时间,且时间优势与任务规模成正比;在调度长度方面,所提算法的平均性能提升了约10％.     

一种面向动态部分可重构片上系统的列表式软硬件划分算法

并行计算是提高系统资源利用率的重要手段,越来越多的多处理器片上系统通过集成具有不同功能特点的处理器来满足不同计算任务的需求.具备动态部分可重构特性的异构多处理器片上系统(Dynamic Partial Reconfiguration-Heteroge-neous Multiprocessor Systems-on-Chip,DPR-HMPSoC)因其并行性好、计算效率高而被广泛使用,而低复杂度和高求解性能的软硬件划分算法是充分发挥其计算性能优势的重要保证.已有的相关软硬件划分算法时间复杂度高,且对DPR-HMPSoC平台的支撑不足.针对上述问题,首先提出了一种列表启发式软硬件划分与调度算法,其通过构建基于任务优先级的调度列表,完成任务的调度、映射、FPGA动态部分可重构区域划分等一系列操作;接着给出了软件应用建模、计算平台建模及所提算法的详细设计方案.仿真实验结果表明,所提算法与混合整数线性规划(Mixed Integral Linear Programming,MILP)和蚁群优化(Ant Colony Optimization,ACO)算法相比,可有效减少求解时间,且时间优势与任务规模成正比;在调度长度方面,所提算法的平均性能提升了约10％.     

多选择软硬件划分问题的计算模型与动态规划算法

软硬件划分是软硬件协同设计的关键环节,划分的结果直接影响目标系统的设计质量。因此,对于一个给定的应用程序,为了使得目标系统快速执行且成本低廉,合理的划分策略十分重要。由于单个任务具有多种不同的硬件实现方式,与传统的单一硬件实现方式的软硬件划分问题相比,多选择的软硬件划分更能客观地反映现实应用。这导致问题的求解更具挑战性,它们已被证明是NP完全问题。基于多核处理器片上系统并针对任务图为二叉树的应用,建立了多选择软硬件划分问题的计算模型,并提出了解决该问题的动态规划算法。实验结果表明,当问题规模适中时,所提动态规划算法能够有效地获得精确解,并展示了算法的计算能力与硬件面积限制之间的关系。     

一种改进的优先级列表任务调度算法

异构多核处理器任务调度是高性能计算领域的重要问题。针对优先级列表调度算法中存在的优先级排序方法失当、调度结果不理想的问题,提出一种改进的优先级列表任务调度算法。该算法对传统优先级列表任务调度中以任务执行时间平均值作为参数的优先级计算方式进行优化,提出一种基于异构核性能差异性、依赖任务特征加权优先级的排序方式。在此基础上,以当前格局下每个任务的向后关键路径执行时间为权值作为任务分配到处理器内核的依据,克服贪心思想在内核选择中带来的局部最优解问题。此外,在任务分配阶段利用任务复制和区间插入技术,缩短任务最早开始时间,提高处理器利用率。实例分析和模拟实验结果表明,该算法可有效降低任务的执行时间,能发挥异构多核处理器优势。     

采用预配置策略的可重构混合任务调度算法

在对可重构硬件资源进行抽象的基础上,采用软硬件混合任务有向无环图来描述应用,提出一种基于列表的混合任务调度算法.该算法通过任务计算就绪顺序及可重构资源状态确定硬件任务的动态预配置优先级,按此优先级进行硬件任务预配置,隐藏硬件任务的配置时间,从而获得硬件任务运算加速.实验结果表明,针对可重构系统中的软硬件混合任务调度,能够有效地降低配置时间对应用执行时间的影响.     

基于网格工作流的列表启发式算法研究

将用户定义的具体网格工作流抽象为DAG图,在DAG图中找到其关键路径,根据关键路径和用户的类型来计算任务的预测执行时间,确定任务的优先级,再比较若干候选资源,选择性价比较高的资源进行任务分配调度算法。     

基于遗传算法的可重构系统软硬件划分

在考虑动态部分重构及重构延时等特征的基础上,采用遗传算法及其与爬山算法的融合实现可重构系统软硬件任务的划分,并采用动态优先级调度算法进行划分结果的评价。实验表明,在可重构系统的资源约束等条件下,算法能够有效地实现应用任务图到可重构系统的时空映射。     

基于网格资源预测的任务优先级调度算法

根据网格工作流中任务的依赖关系和截止时间,以及资源的有效度和MIPS（每秒百万条指令）,提出基于网格资源预测的任务优先级调度算法。把网格任务工作流抽象为有向无环图,找到该工作流的关键路径,计算每个任务的最迟开始执行时间,作为任务的优先级。在算法中考虑用户的要求和资源的类型,以及任务调度失败后重新分配的问题。实验验证了该算法的有效性。     

New Model and Algorithm for Hardware/Software Partitioning

This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.     

Algorithmic aspects for multiple-choice hardware/software partitioning

Hardware–software partitioning (HW/SW) divides an application into software and hardware. It is one of the crucial steps in embedded system design. For a given task, hardware with different areas may provide different execution speeds due to the potential of parallel execution in hardware implementation. Thus, one task may have multiple-choice in hardware implementation according to the available hardware areas. Existing HW/SW partitioning approaches typically consider only a single implementation manner in hardware, overlooking the multiple-choice of hardware implementations. This paper presents a computing model to cater for the HW/SW partitioning problems with the multiple-choice implementation in hardware. An efficient heuristic algorithm is proposed to rapidly generate approximate solution, that is further refined by a tabu search algorithm also customized in this paper. Moreover, a dynamic programming algorithm is proposed for the exact solution of the relatively small problems. Extensive simulation results show that the approximate solutions are very close to the exact ones, and they can be refined by tabu search to the solutions with the error no more than 1.5% for all cases considered in this paper.     

基于放置代价的可重构系统任务统一调度算法

高效的任务调度算法对可重构系统的性能有极大的影响。针对目前可重构系统任务在线调度算法的不足,提出了一种基于放置代价的调度算法。该算法考虑了3种代价,分别为:硬件任务在FPGA上的执行时间、占用的FPGA面积以及FPGA的碎片情况,并且也考虑了软硬件任务的统一调度。在调度过程中,当代价超过设定的阈值时,就拒绝其在FPGA上运行,并由CPU执行其软实现。通过合理地拒绝一些代价较大的任务,能够从整体上提高任务调度成功率。实验表明,同已有算法相比,该算法能够获得更高的任务截止保证率。     

Co-Processor for evolutionary full decision tree induction

In this paper a co-processor for the hardware aided decision tree induction using evolutionary approach (EFTIP) is proposed. EFTIP is used for hardware acceleration of the fitness evaluation task since this task is proven in the paper to be the execution time bottleneck. The EFTIP co-processor can significantly improve the execution time of a novel algorithm for the full decision tree induction using evolutionary approach (EFTI) when used to accelerate the fitness evaluation task. The comparison of the HW/SW EFTI implementation with the pure software implementation suggests that the proposed HW/SW architecture offers substantial DT induction time speedups for the selected benchmark datasets from the standard UCI machine learning repository database.     

Semaphore queue priority assignment for real-time multiprocessorsynchronization

Prior work on real time scheduling with global shared resources in multiprocessor systems assigns as much blocking as possible to the lowest priority tasks. We show that better schedulability can be achieved if global blocking is distributed according to the blocking tolerance of tasks rather than their execution priorities. We describe an algorithm that assigns global semaphore queue priorities according to blocking tolerance, and we present simulation results demonstrating the advantages of this approach with rate monotonic scheduling. Our simulations also show that a simple FIFO usually provides better real time schedulability with global semaphores than priority queues that use task execution priorities     

Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system

There are many design challenges in the hardware-software co-design approach for performance improvement of data-intensive streaming applications with a general-purpose microprocessor and a hardware accelerator. These design challenges are mainly to prevent hardware area fragmentation to increase resource utilization, to reduce hardware reconfiguration cost and to partition and schedule the tasks between the microprocessor and the hardware accelerator efficiently for performance improvement and power savings of the applications.In this paper a modular and block based hardware configuration architecture named memory-aware run-time reconfigurable embedded system (MARTRES) is proposed for efficient resource management and performance improvement of streaming applications. Subsequently we design a task placement algorithm named hierarchical best fit ascending (HBFA) algorithm to prove that MARTRES configuration architecture is very efficient in increased resource utilization and flexible in task mapping and power savings. The time complexity of HBFA algorithm is reduced to O(n) compared to traditional Best Fit (BF) algorithm’s time complexity of O(n²), when the quality of the placement solution by HBFA is better than that of BF algorithm. Finally we design an efficient task partitioning and scheduling algorithm named balanced partitioned and placement-aware partitioning and scheduling algorithm (BPASA). In BPASA we exploit the temporal parallelism in streaming applications to reduce reconfiguration cost of the hardware, while keeping in mind the required throughput of the output data. We balance the exploitation of spatial parallelism and temporal parallelism in streaming applications by considering the reconfiguration cost vs. the data transfer cost. The scheduler refers to the HBFA placement algorithm to check whether contiguous area on FPGA is available before scheduling the task for HW or for SW.     

Efficient heuristic and tabu search for hardware/software partitioning

Hardware/software (HW/SW) partitioning is a crucial step in HW/SW codesign that determines which components of the system are implemented on hardware and which ones on software. It has been proved that the HW/SW partitioning problem is NP-hard. In this paper, we present two approaches for HW/SW partitioning that aims to minimize the hardware cost while taking into account software and communication constraints. The first is a heuristic approach that treats the HW/SW partitioning problem as an extended 0–1 knapsack problem. In the second approach, tabu search is used to further improve the solution obtained from the proposed heuristic algorithm. Experimental results show that the proposed algorithms outperform a recently reported work by up to 28 %.     

高效软硬件划分算法及其提升技术

软硬件划分是软硬件协同设计的关键环节,它决定系统中哪些组件由软件实现,哪些由硬件实现。软硬件划分问题已被证明是NP完全问题。将一类软硬件划分问题看作变异的0-1背包问题,在求解背包问题的算法基础上构造出软硬件划分问题的优质启发解。此外,采用禁忌搜索(Tabu Search)算法对求得的启发解进行改进,在软件开销和通信开销满足一定约束的条件下,使得硬件开销尽可能小。实验结果证明,所提算法对当前最新算法的改进最大可达到28%。     

基于多核处理器的关联任务并行感知调度算法

关联任务在多核处理器上并行调度所产生的通信时延,会对任务调度长度和处理器利用率造成负面影响,为了改善多核系统对关联任务的处理性能,针对关联任务在多核处理器上的调度特点,提出一种并行感知调度算法。计算各任务与终点间的最长路径值,按照该值的降序来分配任务调度次序,在分配处理器内核时兼顾关联度和任务最早可执行时间,设置最佳匹配评价函数。实验结果表明,与busHEFT和DTSV算法相比,该算法具有更短的任务调度时延、更少的通信量以及更高的处理器利用率。