An electrical mechanism for holding time degradation in dynamic MOS RAM's

Holding time degradation due to electrically generated excess minority carriers has been observed in a 16-kbit dynamic MOS RAM. The failure mode is described by two-step impact ionization in a drain depletion region of a transistor and a subsequent diffusion process. Other experiments by a dynamic MOS RAM cell test device, a charge-coupled device, and a He-Ne laser for carder excitation, consistently verify the mechanism which leads to degradation of stored information. In addition, the actual failure map is successfully reproduced by an optical experiment, and also in a computer simulation. Effects of electrical excess minority-carrier generation are discussed from a reliability point of view, particularly for dynamic MOS LSI's.     

Evidence of optical generation of minority carriers from saturated MOS transistors

Minority carrier injection into the substrate by a MOS transistor operating in saturation presents a reliability problem in dynamic memory circuits such as RAM's and CCD's. The effect has been studied by measuring the substrate and drain currents of stressed transistors as a function of gate and drain voltages, firstly by the accumulation of minority carriers in a charge coupled device, and secondly by the direct detection of light from the drain region of a transistor. These results suggest that light emission associated with multiplication in the drain region is more important than the secondary impact ionization mechanism in the generation of minority carriers.     

Impact of silicon nitride CESL on NLDEMOS transistor reliability

Aging of the linear drain current during OFF stress on a N-type lateral drain extended MOS is shown to be induced by the amorphous silicon nitride Contact Etch Stop Layer (CESL). A design of experiment on its PECVD conditions enables to demonstrate that the higher its Si-rich composition or at least of its interface, the higher the degradation. Supported by TCAD simulations, we propose a charge displacement model in the CESL that leads to the depletion of the extended drain region during stress explaining the on-resistance increase monitored by the linear drain current.     

Devices’ optimization against hot-carrier degradation in high voltage pLEDMOS transistor

The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. To decrease the hot-carrier degradation, two methods are proposed to optimize the drift region without additional processes. The novel structure is with a low doped boundary of the drift region and a drift region implanted at intervals by multi-windows, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and TCAD simulations. Out of the simulations results, the length of the low doped boundary and the space between the doping windows of the sub-drifts are discussed, and their effects on the degradation induced by hot carriers has been investigated in detailed. An optimization structure is proposed for the first time.     

Analytical I-V relationship incorporating field-dependent mobility for a symmetrical DG MOSFET with an undoped body

A simple expression explicitly relating the surface potential to the surface electric field of a symmetrical double-gate (DG) MOS capacitor is proposed. The expression does not contain the floating-body potential as an implicit variable. It is used to derive, assuming the validity of the gradual-channel approximation, an analytical model expression for the current-voltage relationship of a DG MOS field-effect transistor. The effects of mobility degradation at high vertical electric field and velocity saturation at high lateral electric field are incorporated. The model expression is continuously valid from the subthreshold to the quasi-linear regimes of operation and up to a well-defined drain saturation voltage. Beyond this saturation voltage, the gradual-channel approximation breaks down within a region near the drain end of the channel. The electric-field distribution within this region is estimated by solving a two-dimensional Poisson's equation. Further implications of the model are derived by simplifying the expression in different regimes of operation using various approximations.     

A method to extract mobility degradation and total seriesresistance of fully-depleted SOI MOSFETs

Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed     

A mobility model for carriers in the MOS inversion layer

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 10⁶cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

The insulated gate tunnel junction triode

The gate modulated voltage breakdown of the drain diode in the MOS transistor is considered and shown to be direct electric field control of a reverse biased surfacep+-njunction. A structure designed to isolate this effect has been suggested by Atalla and experimentally evaluated by Nathanson, et al., and by the authors. The mechanism of operation discussed involves the application of an external electric field normal to the surface of the highly doped side of the junction to produce direct field emission of carriers. The reverse biased low doped side of the junction then acts as a collector of the field-emitted carriers resulting in a net current flow across the junction. Using the Atalla structure, a model is presented and a quantitative theory is developed to explain and predict the device performance. It is found that the actual device may be represented as an MOS transistor in series with an "ideal" field-controlled tunnel junction, and that the performance of the actual device can never be better than that of the limiting MOS transistor. The theoretical characteristics of the ideal field-controlled tunnel junction are derived and found to agree closely with the experimental results. It is shown that, at the present time, the device is limited by the "ideal" tunnel junction region and not by the series MOS transistor.     

Hot-carrier reliability and breakdown characteristics of multi-finger RF MOS transistors

Hot-carrier reliability and drain breakdown characteristics of multi-finger short channel MOS transistors are studied in detail. Several abnormal characteristics were observed. With the aid of numerical simulation, we found that the shared drain and source regions for adjacent gate fingers can lead to current crowding and result in the finger number-dependent current-voltage characteristics. In addition, the high current density spots near the drain region would result in the significant hot-carrier induced transconductance degradation as well as remarkable drain breakdown voltage lowering.     

Source to drain resistance beyond pinch-off in metal-oxide-semiconductor transistors (MOST)

A detailed analysis is performed yielding source to drain resistance of MOS transistors in the saturation region. The analysis is based on a depletion model of the pinched-off region of the channel. Good agreement is found between theory and experimental results obtained onN-channel silicon MOS transistors (channel length ∼5 µ).     

Modelling of channel enhancement effects on the write characteristics of FAMOS devices

Physical modelling of floating-gate avalanche-injection MOS (FAMOS) devices in the program (write) mode is complicated by a feedback effect to the channel from the floating gate. The floating gate takes on a potential by virtue of capacitive coupling to the drain; this induces a channel near the source; the channel injects carriers into the depletion region near the drain and greatly enhances the avalanche multiplication current. This paper presents a simple method for taking account of this effect using empirical data, and thereby arriving at a first-order model of the FAMOS device. Measurements of drain current are subdivided into channel current and avalanche multiplication current, and a constant hot-carrier injection efficiency is assumed. The hot-carrier (avalanche) injection current is associated with a dielectric resistivity, whose dependence on the electric field in the oxide can be approximated by a simple exponential function. Model predictions for the write characteristics of FAMOS devices are in reasonable agreement with experiment.     

Interaction of interface-traps located at various sites in MOSFETs under stress

Interaction of interface traps at different sites in p-MOS transistors under electrical stresses was observed. We report the following phenomenon: generation of interface traps in the basewell-channel (BC) region under Fowler-Nordheim (FN) stress causes reduction and migration of interface traps in the drain junction space charge (JSC) region induced by hot carrier (HC) stress. This phenomenon is tentatively interpreted by a 3-cell difference model of hydrogen release and absorption during interface trap generation and passivation. This effect is important in hot carrier degradation and lifetime projection in MOS transistors.     

1/f noise in MOS devices, mobility or number fluctuations?

Recent experimental studies on 1/f noise in MOS transistors are reviewed. Arguments are given for the two schools of thought on the origin of 1/f noise. The consequences of models based on carrier-number ΔN or mobility fluctuations Δμ on the device geometry and on the bias dependence of the 1/f noise are discussed. Circuit-simulation-oriented equations for the 1/f noise are discussed. The effects of scaling down on the 1/f noise is studied in the ohmic region as well as in saturation. In the ohmic region the contribution of the series resistance often can be ignored. However, in saturation the noise of the gate-voltage-dependent series resistance on the drain side plays a role in lightly doped drain LDD mini-MOST's. Surface and bulk p-channel devices are compared and the differences between n-and p-MOST's often observed is discussed. The relation between degradation effects by hot carriers or by γ-irradiation on the one hand and the 1/f noise on the other is considered in terms of a ΔN or Δμ. Experimental results suggest that 1/f noise in n-MOST's is dominated by ΔN while in p-MOST's the noise is due to Δμ     

The SINFET: a new high conductance, high switching speed MOS-gated transistor

A new MOS power semiconductor device with a very low on-resistance and a switching speed comparable to conventional n-channel power MOSFETs is described. The fabrication process is similar to that of an n-channel lateral DMOS transistor but with the conventional high-low `ohmic? drain contact replaced by a Schottky contact. In operation, the Schottky contact injects minority carriers to conductivity-modulate the n- drift region, thereby reducing the on-resistance by a factor of about ten compared with those of conventional n-channel power MOSFETs of comparable size and voltage capability. Furthermore, since only a small number of minority carriers are injected, the device speed is comparable to conventional n-channel power MOSFETs.     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

Influence of gate oxide breakdown on MOSFET device operation

The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.     

Analysis of the depletion-mode MOSFET including diffusion and drift currents

A four-terminal model for a long-channel depletion-mode MOS transistor including both the diffusion and the drift components of the current along the channel is developed. The theory, which is derived in the gradual channel hypothesis, has been built-up by considering both Poisson's equation and the current-continuity equation. The model is able to describe, without discontinuities, the dc drain current in the enhancement, depletion, and subpinchoff regimes of operation of the device. It is shown that pinchoff and zero drain conductance are naturally achieved as the drain voltage increases, while in the subpinchoff regime the drain current exponentially depends on gate voltage and is mainly due to the diffusion component. Finally, it is found that mobility degradation effects due to the normal component of the electric field can easily be taken into account and it is shown that experimental data favorably compare with the proposed model.     

Holding time degradation in dynamic MOS RAM by injection-induced electron currents

The holding time degradation of a dynamic MOS RAM caused by a peripheral MOS device operated in the saturation region is discussed. It is shown that the process taking place is injection of electrons into a positively biased substrate region from a grounded junction. This junction becomes forward biased due to the resistive potential drop on the substrate caused by the high substrate current of the short-channel MOS device operated in the saturation region. The model presented in the literature of secondary-impact ionization of holes in the depletion-region edge being responsible for the degradation phenomenon is shown to be inconsistent with experimental results and theoretically improbable.