A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Based on a 90-nm silicon-on-insulator (SOI) CMOS process, the floating-body potential of H-gate partially depleted SOI pMOS and nMOS devices with physical gate oxide of 14 /spl Aring/ is compared. For pMOS devices, because the conduction-band electron (ECB) tunneling barrier is lower (/spl cong/3.1 eV), the ECB direct-tunneling current from the n/sup +/ poly-gate beside the body terminal will contribute to a large amount of electron charges into the neutral region and dominate the floating-body potential under normal operations. Conversely, owing to the higher valence-band hole tunneling barrier (/spl cong/4.5 eV), the floating-body potential of nMOS devices is dominated by the band-to-band-tunneling mechanism at the drain-body junction, not the direct-tunneling mechanism.     

Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices

This paper reports the dc performance enhancements of partially depleted (PD) silicon-on-insulator (SOI) devices with lower subthreshold swing and higher driving capability, kink-onset voltage, and transconductance simultaneously. Based on the measured results, by using layout technique, for floating-body PD SOI pMOSFETs with ultrathin gate-oxide thickness, H-gate configuration with the partial n/sup +/ poly-gate shows the best floating-body characteristics as compared to that in T-gate and three-terminal configurations. Owing to the direct-tunneling mechanism in the partial n/sup +/ poly-gate, the conduction-band electron tunneling current will make the floating-body potential biased in strong inversion region raised. In addition, due to the larger oxide voltage drop across the partial n/sup +/ poly-gate in subthreshold region, the valence-band hole substrate current will result in lower floating-body potential. These dc performance enhancements advantage in both digital and analog designs.     

Impacts of gate structure on dynamic threshold SOI nMOSFETs

The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.     

PD SOI nMOSFETs中浮体效应对辐照性能的影响

在SIMOX衬底上制备了H形栅和环形栅PD SOI nMOSFETs,并研究了浮体效应对辐照性能的影响.在106rad(Si)总剂量辐照下,所有器件的亚阈特性未见明显变化.环形栅器件的背栅阈值电压漂移比H型栅器件小33%,其原因是碰撞电离使环形栅器件的体区电位升高,在埋氧化层中形成的电场减小了辐照产生的损伤.浮体效应有利于改进器件的背栅抗辐照能力.     

Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs

H-gate and closed-gate PD SOI nMOSFETs are fabricated on SIMOX substrate,and the influence of floating body effect on the radiation hardness is studied.All the subthreshold characteristics of the devices do not change much after radiation of the total dose of 1e6rad(Si).The back gate threshold voltage shift of closed-gate is about 33% less than that of Hgate device.The reason should be that the body potential of the closed-gate device is raised due to impact ionization,and an electric field is produced across the BOX.The floating body effect can improve the radiation hardness of the back gate transistor.     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs

The hysteresis effect between forward and reverse drain-source voltage (V_DS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (V_TH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (V_DS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high V_DS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors

In this paper, low-frequency noise (LFN) in N- and P-channel dynamic-threshold (DT) MOSFETs on Unibond substrate (SOI) is thoroughly investigated and, especially, an improved formulation of classical McWhorter’s noise model is proposed. In order to confirm our approach, an experimental comparison between body tied and DTMOS on SOI substrate has been achieved in terms of LFN behaviour. Furthermore, two different types of DTMOS transistors have been used: with and without current limiter. The LFN in DTMOS is analysed in ohmic and saturation regimes and the impact of the use of a current limiter (clamping transistor) is thoroughly analysed. An explanation based on floating body effect inducing excess noise is also proposed.     

工作在动态阈值MOS的特性研究

通过将衬底和栅极连接在一起实现了MOSFET的动态阈值,DTMOS与标准的MOSFET相比具有更高的迁移率,在栅极电压升高时DTMOS阈值电压会随之降低,从而获得了比标准的MOSFET大的电流驱动能力。DTMOS是实现低电压、低功耗的一种有效手段。     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V