条件推测性十进制加法器的优化设计

随着商业计算和金融分析等高精度计算应用领域的高速发展,提供硬件支持十进制算术运算变得越来越重要,新的IEEE 754-2008浮点运算标准也添加了十进制算术运算规范。该文采用目前最佳的条件推测性算法设计十进制加法电路,给出了基于并行前缀/进位选择结构的条件推测性十进制加法器的设计过程,并通过并行前缀单元对十进制进位选择加法器进行优化设计。采用Verilog HDL对32 bit, 64 bit和128 bit十进制加法器进行描述并在ModelSim平台上进行了仿真验证,在Nangate Open Cell 45nm标准工艺库下,通过Synopsys公司综合工具Design Compiler进行了综合。与现有的条件推测性十进制加法器相比较,综合结果显示该文所提出的十进制加法器可以提升12.3%的速度性能。     

基于Sklansky结构的24位并行前缀加法器的设计与实现

针对串行进位加法器存在的延时问题,采用一种基于Sklansky结构的并行前缀加法器,通过对并行前缀加法器各个模块进行优化,设计实现了一个24位并行前缀加法器。通过与24位串行进位加法器进行延时比较,结果表明,Sklansky并行前缀结构的加法器,能有效提高运算速度。     

一种结构新颖的流水线Booth乘法器设计

在对传统Booth乘法器研究的基础上,介绍了一种结构新颖的流水线型布什(Booth)乘法器。使用基-4 Booth编码、华莱士树(Wallace Tree)压缩结构、64位Kogge-Stone前缀加法器实现,并在分段实现的64位Kogge-Stone前缀加法器中插入4级流水线寄存器,实现32 t×32 bit无符号和有符号数快速乘法。用硬件描述语言设计该乘法器,使用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行验证,并采用SMIC 0.18 μm CMOS标准单元工艺对该乘法器进行综合。综合结果表明,电路的关键路径延时为3.6 ns,芯片面积＜0.134 mm,功耗＜32.69 mW。     

对数跳跃加法器的静态CMOS实现

介绍了一种32位对数跳跃加法器结构.该结构采用EL M超前进位加法器代替进位跳跃结构中的组内串行加法器,同EL M相比节约了30 %的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用L ing算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现“与-异或”功能;1.0 μm CMOS工艺实现的32位对数跳跃加法器面积为0 .6 2 mm2 ,采用1μm和0 .2 5 μm工艺参数的关键路径延迟分别为6 ns和0 .8ns,在10 0 MHz下功耗分别为2 3和5 .2 m W.     

对数跳跃加法器的静态CMOS实现

介绍了一种32位对数跳跃加法器结构.该结构采用ELM超前进位加法器代替进位跳跃结构中的组内串行加法器,同ELM相比节约了30%的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用Ling算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现"与-民或"功能;1.0μm CMOS工世实现的32位对数跳跃加法器面积为0.62mm2,采用1μm和0.25μm 工世参数的关键路径延迟分别为6ns和0.8ns,在100MHz下功耗分别为23和5.2mW.     

一种适合VLSI实现的快速加法器

本文提出一种规整结构超前进位加法器,其加法时间与位数的对数成比例;而且其结构规整、逻辑简单、互连容易。SPICE模拟表明,采用2μm CMOS工艺的16位加法器最坏情况延时为5.4ns,并具有位数加倍延时仅增加1.2ns的扩展特性。它可以方便地用全定制或半定制等VLSI设计方法实现。     

支持短向量的32位快速加法器设计

研究和设计了一种面向多媒体应用的32位短向量快速加法器,该加法器以SK型并行前缀加法器为基础,通过有效控制进位链,实现了同时执行4个基于字节的加法,或者2个基于半字的加法,或者1个基于字的加法,或者1个基于单精度浮点数的比较运算.综合结果表明,此设计方法同传统的设计方法相比,电路面积接近,时序提高了10%,总体性能较优.     

基于RNS算法的高阶FIR滤波器设计

以{2n－1,2n,2n+1,2ⁿ－¹－1,2ⁿ⁺¹－1}为余数基,在余数系统(RNS)的基础上设计了一种128抽头有限脉冲响应(FIR)滤波器。针对大位宽输入,利用基于华莱士(Wallace)树结构的纯组合逻辑电路,实现了二进制到余数的转换。相较于一般抽头中乘法器级联加法器的结构,设计的乘累加(MAC)单元将加法运算合并到部分积求和中,减少了一级模加法器,使得电路延时进一步减少。此外,通过对进位保留加法器(CSA)的中间结果取模,避免了加法运算引起的位宽增加,从而降低了整个运算的复杂度。电路在FPGA上设计实现。实验结果表明,该滤波器的延时为3.55 ns,功耗为2 585 mW,消耗的硬件资源明显降低。     

一种改进的基于Kogge-Stone结构的并行前缀加法器

基于并行前缀算法的Kogge-Stone结构,通过改进其结构层次上的逻辑电路,提出一种改进的并行前缀加法器.与传统电路相比,该加法器不仅可以减小面积、功耗和延时,而且随着位宽的加大其优势更加明显,是适用于宽位的并行前缀加法器.     

模2~n±1乘法的可重构设计与实现

论文提出了一种可同时实现模2~n±1乘法的算法及其VLSI结构。通过对常规并行前缀加法器和乘法器的改造,在实现普通加法和乘法的基础上增加少量逻辑,实现了模2~n±1乘法(n=8、16、32)。较之同类设计,该设计实现了对常规加法器和乘法器资源的高度重用,而且性能较高。     

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata(QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder(ESDBA) is 26% faster than the carry flow adder(CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder(EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead(CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of(N-1)+3.5 clock cycles compared to the N*One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.     

A fully redundant decimal adder and its application in parallel decimal multipliers

Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast computation of the transfer digit and interim sum. In the proposed fully redundant adder (VS semi-redundant ones such as decimal carry-save adders) both operands and sum are redundant decimal numbers with overloaded decimal digit set [0, 15]. This adder is shown to improve upon the latest high performance similar works and outperform all the previous alike adders. However, there is a drawback that the adder logic cannot be efficiently adapted for subtraction. Nevertheless, this adder and its restricted-input varieties are shown to efficiently fit in the design of a parallel decimal multiplier. The two-to-one partial product reduction ratio that is attained via the proposed adder has lead to a VLSI-friendly recursive partial product reduction tree. Two alternative architectures for decimal multipliers are presented; one is slower, but area-improved, and the other one consumes more area, but is delay-improved. However, both are faster in comparison with previously reported parallel decimal multipliers. The area and latency comparisons are based on logical effort analysis under the same assumptions for all the evaluated adders and multipliers. Moreover, performance correctness of all the adders is checked via running exhaustive tests on the corresponding VHDL codes. For more reliable evaluation, we report the result of synthesizing these adders by Synopsys Design Compiler using TSMC 0.13 μm standard CMOS process under various time constrains.     

高性能并行全冗余十进制乘法器的设计

商业计算、金融分析等领域对高精度计算的需求对硬件十进制运算提出了越来越高的要求.已有的全冗余十进制乘法器由于全冗余加法器的结构复杂,已经给其性能的提升造成了瓶颈.本文优化设计了基于超载十进制数集（Overloaded Decimal Digit Set,ODDS）的全冗余ODDS加法器以降低其复杂度,并设计了一种新的基于该加法器的十进制压缩树模块.本文在部分积产生模块采用有符号的基-10编码和冗余的二-十进制（Binary Coded Decimal,BCD）编码快速产生十进制部分积.在最终积产生模块采用优化的编码转换电路快速产生BCD-8421乘积.实验结果显示所设计的并行全冗余十进制乘法器速度较快、面积较小.     

FPGA-specific decimal sign-magnitude addition and subtraction

The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten’s complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.     

Implementation of a self-resetting CMOS 64-bit parallel adder withenhanced testability

This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22°C with V_dd=2.5 V) and 300 mW. The adder core size is 1.6×0.275 mm². The process technology used was the 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs     

一种稀疏树加法器及结构设计

提出了一种稀疏树加法器,该加法器基于并行前缀加法器,以预处理和后处理阶段的面积和延迟换取并行前缀进位阶段的面积和延迟,可针对大多数并行前缀加法器进行改进,在较长操作数相加时可节省面积同时减小关键路径延迟。以几种并行前缀加法器Sldarisky、Brent—Kung、Kogge—Stone和Han—Carlson为例,对他们的面积和延迟进行了理论分析。在本文的最后用硬件描述语言实现了Sklansky加法器。     

一种基于简单移位的二——十进制相互转换算法

十进制码(BCD)与二进制代码相互转换的问题的研究,主要偏重于软件实现.本文基于数制变换的基本原理,提出了移位为基础的、适合硬件实现的转换算法.并根据该算法,构造了63位二进制与十进制代码的转换器.同时,对该算法又进行了扩充,提出基2^<em>r移位的算法,进一步提高性能.从性能的比较可以看出,该算法速度高,逻辑简单,非常适合实时性要求较强的嵌入式领域应用.     

Memristor based N-bits redundant binary adder

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the theoretical advantages of the redundant binary system, and to eliminate the carry (borrow) propagation using signed digit representation. The advantage of carry elimination in the addition process is that it makes the speed independent of the operands length which speeds up all arithmetic operations. One memristor is sufficient for both the addition process and for storing the final result as a memory cell. The adder operation has been validated via different cases for 1-bit and 3-bits addition using HP memristor model and PSPICE simulation results.