工件台方镜轻量化结构的拓扑优化设计

为满足工件台方镜的高模态及高轻量化的要求,在设计过程中充分考虑其材料的选择,并重点引入拓扑优化方法。依据变密度法建立SIMP模型,在方镜的特定约束工况下,以结构第1阶模态为设计约束,最小体积为设计目标进行迭代,得到了较好的轻量化结构。并对拓扑优化后的结构与常规结构进行了分析对比,结果表明:拓扑优化的结构第1阶模态为710.5 Hz,提高+4.5%。同时,在轻量化率上提高了+8.2%。因此,拓扑优化的结果要优于常规结构方式,体现出了拓扑优化方法在工件台结构设计过程中具有重要的实际应用价值。     

红外光电系统机械固定件的拓扑优化设计

红外光电系统机械件复杂度高,在满足稳定性要求的前提下,对结构的轻量化有着更急迫的需求。本文采用ANSYS拓扑优化方法对某红外光电系统进行拓扑优化设计,并以电源固定件为例,以结构柔度最小为设计目标,单元密度为设计变量,实现30%的体积约束,并对拓扑优化的结果进行模型重构。与初始经验设计方案对比,优化重构后的固定件减重37.8%,且结构的刚度和强度均得到了提升。进而表明,拓扑优化方法可以为红外光电系统结构的轻量化设计提供有利的借鉴。     

Hyperworks在床身动静态分析及优化中的应用

床身刚度是影响高速机床加工精度的一个重要因素。针对床身刚度是否满足加工精度要求的问题,以双直线电机高速进给的铣床床身为研究对象,采用有限元方法建立床身的动力学模型,并利用有限元软件Hyperworks对床身进行动静态分析,找出该床身的动静态性能薄弱部位,利用Hyperworks的Optistruct拓扑模块对床身进行结构优化。优化后的结果表明,3个方向静刚度平均提高了1 000 N·μm-1,固有频率提高了约30 Hz,x和z向频率响应的振幅约减小50%,为同类型结构设计提供一定的参考。     

机载红外系统主反射镜的拓扑优化设计

反射镜轻量化设计一直是光机结构设计领域的一项挑战性课题。针对某机载红外光学系统的主反射镜,提出了一种基于SIMP拓扑优化方法的反射镜轻量化设计流程,建立了反射镜拓扑优化的数学模型,以最小化镜体自重和抛光载荷作用下的镜面矢高位移RMS值为优化目标,同时考虑对称约束和拔模约束,对反射镜进行了拓扑优化设计。根据拓扑优化结果设计了新的反射镜轻量化结构,并将其与传统结构进行了对比。采用拓扑优化方法设计的反射镜具有更高的轻量化率,同时能够获得较高的面形精度。     

深空探测相机超轻主支撑结构优化设计

根据深空探测相机轻质高刚度、高性能的要求,设计了一种超轻主支撑结构。深空探测相比于地球探测环境更加严苛,主支撑结构作为主承力结构,其在发射、在轨环绕阶段都应具有高稳定性,来保持各光学元件之间的相对位置不变。与传统方法相比,文中采用拓扑优化得到清晰的主支撑结构的最佳传力路径,然后通过尺寸优化来提高主支撑结构基频。最后进行轻量化设计,其前后框架结构轻量化率达到90%以上。仿真分析和试验结果表明,主支撑结构满足公差要求且基频（80.264 Hz）远远高于整星一阶频率,应用光学测量的方法振前、振后前框架相对于后框架倾角为3、0.3,满足光学系统的公差要求,具有较好的稳定性。大量级力学试验后系统的波像差/14,满足光学系统成像质量要求。     

基于Hyper Works的6杆并联机床的优化设计

针对并联机床加工过程中发生共振导致机构变形进而影响零件加工精度的问题,文中以6杆并联机床为研究对象,采用拓扑优化的方法对并联机床床身进行优化。首先确定床身的优化部位为立柱、横架和定台,运用HyperWorks中拓扑优化模块对其优化,通过添加一定的加强筋来整修优化立柱和横架,对立柱的筋板尺寸进一步优化。优化后运用模态分析和谐响应分析进行整机验证,对比优化前后模型,发现优化后的模型总质量减少了17.8%,前三阶共振频率分别增加了19.56%、20.62%、0.091%,共振峰值在X、Y、Z方向降低了49.454%、29.036%、0.0078%。对结果分析可知优化后的并联机床在加工中避免了共振的发生,其加工精度得到了提高。     

紫外-近红外高光谱探测仪扫描镜拓扑优化设计

为了研究某紫外-近红外高光谱探测仪扫描镜工作在运动状态的轻量化问题,提出了以扫描镜动态面形为设计约束的拓扑优化方法.对设计约束进行了有效的简化,降低了计算的复杂程度.使用拓扑优化方法得到了在转动条件下扫描镜的最优轻量化形式.分析结果表明,拓扑优化后的扫描镜轻量化率为47.3%,动态面形PV值和RMS值分别为19.36 nm和5.65 nm,比优化前分别提高了18.45%和17.40%,同时,扫描镜的一阶频率提高了113.8 Hz.分析结果说明了以动态面形为设计约束进行扫描镜拓扑优化的合理性.     

机载红外成像系统主支撑结构新型轻量化设计方法与应用

由于载机负载有限,质量一直是机载成像系统结构设计时的关键指标。主支撑结构作为机载成像系统中光学系统的主承力结构,必须进行轻量化设计。但是,以往机载成像系统主支撑结构轻量化设计方法主要包括选择比刚度高的金属材料、优化框架结构布局、调整壁厚、增加减重槽等具体措施。由于金属材料的密度和线膨胀系数较高,这种轻量化设计方法的轻量化程度不高,且有时无法满足高精度光学系统无热化设计的要求。因此,提出了一种复合材料与金属材料相结合的新型轻量化设计方法,利用更低密度、更低线膨胀系数的碳纤维复合材料作为主支撑结构成型材料,钛合金作为对外接口材料,并以质量最轻为目标、基频为约束进行了参数优化设计,最后采用预浸料制造与铺放方法获得了更高轻量化、更优尺寸稳定性的主支撑结构。通过数值计算、仿真分析与振动试验对新方法的有效性进行了验证,结果表明:新型轻量化主支撑系统基频为425 Hz;质量为10.5 kg,轻量化率为33.5%;60 ℃均匀温升时轴向光学间隔变化量为0.021 mm,降低了84.9%。研究结果表明:新型轻量化设计方法合理、有效,解决了结构轻量化与光学无热化设计的难题,并应用到长焦距大口径机载红外成像系统中。     

大口径望远镜次镜系统的拓扑优化设计

针对地基大口径望远镜次镜系统加工精度和装调精度的要求，提出了基于拓扑优化的次镜系统结构设计方法。该方法利用变密度的拓扑优化思想，将次镜系统的Spider结构和Serrurier桁架的设计域限定为基结构，以期望方向的变形最小，通过材料的去留决定结构的最终形状和尺寸。首先，以相对密度为设计变量，Spider结构以1阶振型和重力方向变形为设计约束，桁架以X向和Y向变形为设计约束，建立各结构的拓扑优化模型；然后，以拓扑优化所得构型为基础，利用Workbench进行优化迭代；最后，设置优化参数，采用有限元法进行动静刚度分析和优化。结果显示4 m望远镜次镜系统的1阶谐振为22.7 Hz，光轴指向天顶和水平时重力方向偏移分别为-0.173 mm和-0.195 mm，并且Spider结构和Serrurier桁架的轻量化率超过30%。该结果验证了文中方法的有效性。     

空间引力波望远镜主镜组件的结构设计

针对空间引力波望远镜皮米量级的极高光程稳定性需求,对系统中主镜组件进行了优化设计。采用微晶玻璃（Zerodur）作为反射镜材料,支撑结构材料为铟钢（4J36）。首先,通过对反射镜参数的优化,使其在保证面形精度的同时镜体轻量化率达到了72%。然后,设计了一种双轴联杆型Bipod柔性反射镜支撑结构,并采用了侧面三点支撑的形式。以保证有效的支撑刚度及卸载效果为目的,建立了柔性铰链的数学模型,并基于Matlab对其尺寸参数进行了优化。最后,对优化设计后主镜组件进行了模态分析及振动试验,并完成了在轨分析与波前质量计算。结果显示,主镜组件的一阶固有频率为373 Hz,与试验结果的相对误差为3.5%;在轨环境下主镜面形精度达到8.9 nm（RMS）;波前精度为/5（=1 064 nm）。表明该反射镜组件满足设计指标要求。     

Enhancing sensitivity-based power reduction for an industry IC design context

For many years, discrete gate sizing has been widely used for timing and power optimization in VLSI designs. The importance of gate sizing optimization has been emphasized by academia for many years, especially since the 2012/2013 ISPD gate sizing contests [1, 2]. These contests have provided practical impetus to academic sizers through the use of realistic constraints and benchmark formats. At the same time, due to simplified delay/power Liberty models and timing constraints, the contests fail to address real-world criteria for gate sizing that are highly challenging in practice. We observe that lack of consideration of practical issues such as electrical and multi-corner constraints – along with limited sets of benchmarks – can misguide the development of contest-focused academic sizers. Thus, we study implications of the “gap” between academic sizers and product design use cases. In this paper, we note important constraints of modern industrial designs that are generally not comprehended by academic sizers. We also point out that various optimization techniques used in academic sizers can fail to offer benefits in product design contexts due to differences in the underlying optimization formulation and constraints. To address this gap, we develop a new robust academic sizer, Sizer, from a fresh implementation of Trident [3]. Experimental results show that Sizer is able to achieve up to 10% leakage power and 4% total power reductions compared to leading commercial tools on designs implemented with foundry technologies, and 7% leakage power reduction on a modern industrial design in the multi-corner multi-mode (MCMM) context.     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

Particulate Coatings with Optimized Haze Properties

The haze factor, which describes the fraction of light that is scattered when passing through a transparent material, is of general importance for any optical device, from milk glass shielding visibility while providing ambient lighting to solar cells that are optimized by sophisticated light management layers. Often, such active layers are fabricated from particulate materials that are deposited as thin films on a substrate. Here, the effect of structural arrangement, position, and orientation of particles on the resulting haze factor is investigated. A mathematical optimization model that iteratively alters the particle layer structure to maximize or minimize the haze factor for a range of optimization scenarios is designed. Colloidal self‐assembly techniques are then used to replicate typical particle structures found in the optimized designs and correlate the macroscopically measured haze values to the predictions of the optimization. The results indicate general design rules that control the haze value in particle layers. Non close‐packed structures with distributed scatterers and high degrees of order provide minimal haze values while chain‐like arrangements and small clusters maximize the haze of a particle layer. Finally, the findings are transferred to metal nanohole films as model transparent electrodes with controlled haze values.     

大马士革铜阻挡氮化硅薄膜沉积工艺优化研究

在铜大马士革（Damascene）工艺中,为避免由于铜向FSG中扩散所致电迁移的问题,需要在铜表面沉积一层氮化硅作为隔离铜和随后的介电材料的直接接触,通常人们使用HDP—CVD来沉积该氮化硅层。但针对HDP—CVD沉积速率快和工艺设备成本高等问题,文中研究了一种优化了的PECVD氮化硅沉积工艺来取代HDP—CVD氮化硅工艺。优化主要包含硬件改进和工艺参数调整。硬件改进主要通过引入锥形阴极盘面代替传统的直通形阴极盘面,以实现气体分子的更有效电离。在工艺参数上从RF功率、SiH4流量等方面也有所调整。优化后形成的氮化硅薄膜与HDP—CVD氮化硅薄膜性能非常接近,完全符合大马士革工艺的要求。同时氮化硅薄膜的沉积速率也有明显提高,工艺成本随之降低。     

二氧化碳探测仪镜筒结构的多目标优化设计(英文)

为满足镜筒结构高强度、轻量化及良好的热环境适应性的要求,研究了多工况下同时考虑结构刚度和一阶固有频率的多目标优化问题。首先,基于变密度连续体结构拓扑优化方法,采用加权和法和靶向量法定义了多工况下多目标优化函数;然后进行了镜筒的优化设计。整个优化设计包括拓扑优化和厚度优化两部分。在拓扑优化中,以刚度和频率最大为目标函数,得到了满足要求的镜筒结构材料的最佳分布,并以此为依据,完成了镜筒结构的三维建模;以拓扑优化所得结构的柔度值和一阶频率为约束,质量最小为目标函数,对镜筒结构各厚度进行了优化。优化设计结果表明,镜筒质量由18.63 kg减少至12.46 kg;重力作用下最大变形由0.013 mm减少至0.001 9 mm;热载荷作用下最大变形由0.098 mm减少至0.062 mm;一阶固有频率从65.6 Hz提高至189.83 Hz。该优化设计方法有效缩短了设计周期,提高了镜筒结构的性能,满足了系统设计要求。     

Statistical Timing Yield Optimization by Gate Sizing

In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS'85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30% on the average, over deterministic timing optimization for at most 10% area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for iso-area solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13-mum technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization     

区间长度可变的反向混沌优化算法

针对现有算法在大空间和高维度寻优存在效率较低的问题,提出一种区间长度可变的反向混沌优化算法,并证明了该算法以概率1收敛于全局最优解.算法采用区间长度可变的反向优化策略,利用反向优化方法增大算法进化过程的多样性,使优化的变量区间不断减小.同时,提出基于Fuch混沌映射的反向混沌优化策略增大算法逃逸局部极值的能力,以及两级优化策略提高算法执行后期的寻优精度.通过22个基准函数测试结果表明,本文提出的算法与改进的混沌优化算法以及其他智能优化算法相比,其搜索的综合性能要优于其他算法.