Sensing behavior and mechanism of titanium dioxide-based MOS hydrogen sensor

A Pd/TiO₂/Si MOS sensor (Pdtisin sensor) is proposed for the detection of hydrogen gas. The sensor is fabricated on a p-type 1 1 1 silicon wafer having resistivity of 3–6 Ω cm. The thickness of TiO₂ in this structure is about 600 nm. The capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics of the device is observed on the exposure of hydrogen gas at room temperature. The mechanism of hydrogen sensing of titanium dioxide-based MOS sensor (MOS capacitor) has been investigated by evaluating the change in flat-band voltage (V_FB) and fixed surface state density of the device in presence of hydrogen gas. The device exhibits very large parallel shift in C–V as well in G–V characteristics. The possible mechanism on Pd/TiO₂ and TiO₂/Si surface in presence of hydrogen gas has been proposed. The response and recovery time of the device is also measured at room temperature.     

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I–V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p⁺–n⁺ diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I–V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

A Compact Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design

A silicon-based nanowire FET (SNWT) compact model is developed for circuit simulation. Starting from the solution of Poisson's equation, an accurate inversion charge expression is derived for SNWTs with arbitrary body doping concentration. The drain current, transconductance, output conductance, terminal charges, and capacitances are then calculated based on fundamental device physics. Short-channel and quantum effects have been included in the model in a self-consistent way. Comparison between the numerical simulation and analytical calculation shows that the proposed model is valid for all operation regions of SNWTs with different dimensions and channel doping. The model has been implemented in circuit simulators by Verilog-A, and its application in circuit simulation is also demonstrated.      

HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors

The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed. In addition to initial fast degradation and quick saturation of NBTI stress behavior, non-negligible impacts of electron traps on the stress/recovery characteristics in p-SNWTs with metal gate is found and characterized with a kind of combined I_g–I_d RTN technique. The NBTI behavior is modeled taking account of the impacts from unique structural nature of GAA SNWTs. NBTI induced performance degradation of the typical nanowire-based circuits is estimated based on the proposed model. In addition, stochastic degradation induced by single/few trap in the thin-body SNWTs is observed and analyzed.     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

Breakdown degradation associated with elementary screw dislocations in 4H-SiC pn junction rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector>2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector=1c with no hollow core) in densities on the order of thousands per cm², nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current–voltage (I–V) characteristics of 4H-SiC p⁺n diodes. First, synchrotron white beam X-ray topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p⁺n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I–V knee, and no visible concentration of breakdown current. In contrast, devices that contained at least one elementary screw dislocation exhibited 5–35% reduction in breakdown voltage, a softer breakdown I–V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C–V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C–V curves agree with the recently published data of implanted gate devices.     

A novel linearly tunable butterfly-shape MEMS capacitor

A new MEMS tunable capacitor with linear capacitance–voltage (C–V) response is introduced. The design is developed based on a parallel-plate configuration and uses the structural lumped flexibility and geometry optimization to obtain a linear response. The moving electrode is divided into two segments connected to one another by a torsional spring. There are extra beams located between the two plates, which constrain the displacement of the moving plate. The resulting nonlinear structural rigidity provides the design with higher tunability than the parallel-plate ones. Furthermore, because the plate's displacement is controlled, the shape of C–V curve changes in such a way that high linearity is achieved. The proposed design can be fabricated by a three-structural-layer process such as PolyMUMPs. The results of analytical solution and experimental measurements verify that the new capacitor can produce tunability of over 100% with high linearity. The introduced design methodology can further be extended to flexible plates and beams to obtain smooth C–V curves.     

Electrical properties of W/Si interfaces with embedded Ge/Si islands

In this work, we investigated electrical and morphological properties of W/p-type Si Schottky diodes with intentional inhomogeneities introduced by macroscopic Ge-islands embedded beneath the interface. The Si-cap layer thickness (or the island-distance to the interface) was progressively reduced by successive chemical etching cycles. Electrical characterizations were achieved through reverse current–voltage (I–V) at room temperature and forward I–V measurements as a function of the temperature. In parallel, Rutherford backscattering spectroscopy analyses were performed to follow the Si-cap/Ge islands chemical thinning down with increasing the number of etching cycles. In addition, the comparison of topographical and electrical properties of the etched silicon-cap layer was carried out by conductive atomic force microscopy analyses with a nanometer-scale resolution. Our results indicate that the areas on the top of islands exhibit lower resistance than those which covered the wetting layer. This lateral variation of resistance at the surface of the semiconductor may correspond to Schottky barrier height inhomogeneities observed on broad area I–V characteristics of Schottky contacts.     

Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I–V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10–40 GHz showed the conductance modulation by drain–source voltage. These results indicate the existence of plasma wave interactions.     

High stability and low driving voltage green organic light emitting diode with molybdenum oxide as buffer layer

Green organic light emitting diodes (OLEDs) with copper phthalocyanine (CuPc), 4,4′,4″-tris[3-methylphenyl(phenyl)amino]triphenymine (m-MTDATA) and molybdenum oxide (MoO_x) as buffer layers have been investigated. The MoO_x based device shows superior performance with low driving voltage, high power efficiency and much longer lifetime than those with other buffer layers. At the luminance of 100 cd/m², the driving voltage is 3.8 V, which is 0.5 V and 2.2 V lower than that of the devices using CuPc (Cell-CuPc) and m-MTDATA (Cell-m-MTDATA) as buffer layer, respectively. Its power efficiency is 13.6 Lm/W, which is 38% and 30% higher than that of Cell-CuPc and Cell-m-MTDATA, respectively. The projected half-life under the initial luminance of 100 cd/m² is 42,400 h, which is more than 3.8 times longer than that of Cell-m-MTDATA and 24 times that of Cell-CuPc. The superior performance of Cell-MoO_x is attributed to its high hole injection ability and the stable interface between MoO_x and organic material. The work function of MoO_x measured by contact potential difference method and the J–V curves of “hole-only” devices indicate that a small barrier between MoO_x/N,N′-di(naphthalene-1-y1)-N,N′-dipheyl-benzidine (NPB) leads to a strong hole injection, resulting in the low driving voltage and the high stability.     

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top–down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.      

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

Performances of novel Pd/Sn and Pd/Sn/Au ohmic metallizations to n-GaAs

Performance of novel Pd/Sn and Pd/Sn/Au Ohmic metallizations to n-GaAs have been investigated. Metallizations were deposited using a resistance heating evaporator and annealings were performed utilizing a conventional graphite strip annealer (cGSA). Metallization samples were characterized using scanning tunneling microscopy (STM), secondary ion mass spectrometry (SIMS) and current–voltage (I–V) measurements. Contact resistivities, ρ_c, of the metallizations were measured utilizing conventional transmission line model (cTLM) method. Novel Pd/Sn and Pd/Sn/Au Ohmic contacts exhibit better thermal stability compared to non-alloyed Pd/Ge metallization. In order to investigate the effectiveness of novel Pd/Sn and Pd/Sn/Au Ohmic metallizations in device applications, gallium arsenide metal-semiconductor field-effect transistors (GaAs MESFETs) have been fabricated. MESFETs fabricated with Pd/Sn/Au Ohmic contacts show a extrinsic transconductance, g_me, of more than 133 mS/mm for a gate length, L_G, of 2 μm.     

Optically controlled current-voltage characteristics of ion-implanted MESFETs

Optically controlled MESFETs are useful as optical devices for optical communications, and as photodetectors. In this paper, a theoretical model for the I–V characteristics of these MESFETs is presented. The model considers the nonuniform Gaussian doping for ion-implanted channels. It takes both the photogenerated carriers as well as the doping generated residual carriers into account. It is noted that the density of photogenerated carriers in the channel due to diffusion is much less than that due to drift. Treatment both under gradual channel approximation and saturation velocity approximation has been presented. The gradual channel and the velocity saturation approximations are applied to study the I–V characteristics of long-channel and short-channel MESFETs, respectively. Results for both long-channel and short-channel MESFETs indicate that drain saturation current and transconductance can be improved by properly fixing the optical flux, and the absorption coefficient of the material.     

A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

In this article, we have used quantum and semiclassical models to analyse the electrical characteristics of gate all around silicon nanowire transistor (GAA SNWT). A quantum mechanical transport approach based on non-equilibrium Green's function (NEGF) method with the use of mode space approach in the frame work of effective mass theory has been employed for this analysis. Semiclassical drift diffusion mode space (DDMS) approach has also been used for the simulation of GAA SNWT. We have studied the short-channel effects on the performance of GAA SNWT and evaluated the variation of the threshold voltage, the subthreshold slope (SS), the leakage current and the drain-induced barrier lowering (DIBL) when channel length gets shorter. The results showed that quantum mechanical effects increase the threshold voltage and decrease the leakage current, whereas it has also an impact on the SS and DIBL. We have also investigated the effects of high-κ materials as gate dielectric on the device performance.     

A new empirical large-signal model for enhancement-mode AlGaAs/InGaAs pHEMTs

We propose a new large-signal model for AlGaAs/InGaAs pHEMTs, which can simulate the device microwave output power, non-linear characteristics at arbitrary bias points. This model includes a new drain current equation, which is extracted from its derivatives. In addition, gate-to-source and gate-to-drain capacitances are also characterized versus the function of gate and drain biases. The parameter extraction procedure is addressed for the enhancement-mode pHEMTs, which offers an attractive solution for handset power amplifier application because of its positive bias characteristics. Finally, measured and model-predicted dc I–V, S-parameters, and power performance have been compared.