New experimental findings on hot carrier effects in sub-0.1 μmMOSFET's

The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V_gmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of V_gmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range     

Substrate current model for submicrometer MOSFETs based on meanfree path analysis

The nonequilibrium effects of hot carriers are investigated to analyze avalanche generation for submicrometer MOSFET devices. A simple analytical expression for the impact ionization utilizing the mean free path concept is developed. It is incorporated into a conventional drift-diffusion equation solver (PISCES) to obtain the substrate current in submicrometer MOSFET devices. The transconductance for high drain bias and breakdown conditions are analyzed based on the proposed impact ionization model     

Low temperature characterization of silicon CMOS devices

A brief review of the main physical results concerning the low temperature characterization of Si CMOS devices is presented. More specifically, the carrier mobility law, saturation velocity, short channel effects, impact ionization phenomenon, hot carrier effects and parasitic leakage current are discussed.     

Anomalous hot carrier degradation of nMOSFET's at elevatedtemperatures

An anomalous behavior of nMOSFET's hot carrier reliability characteristics has been investigated at an elevated temperature for the first time. Although the degradation of linear drain current is significantly reduced with increasing stress temperature, the degradation of saturation drain current is enhanced for high temperature stress. This behavior can be explained by the reduction of the velocity saturation length at an elevated temperature, which increases the net amount of interface states that can influence the channel current. This anomalous behavior causes a significant impact on the device reliability for future deep submicrometer devices at high operating temperatures     

Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm²/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm²/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages.     

Full-band Monte Carlo investigation of hot carrier trends in thescaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated     

Electron transport and ionization in silicon at high fields

The saturated drift velocity measured for electrons at high fields is inconsistent with Shockley's model for impact ionization in silicon. It is explained in terms of a field-dependent mean free path for high energy phonon creation in the electric field direction, electrons creating a high energy phonon as soon as they have acquired sufficient energy from the field. Assuming that the electron wavepacket travels at the saturated drift velocity without dispersion, it can be shown that the increased scattering rate at high fields must result in a large spread in the carrier energy. If a drifted Maxwellian distribution is assumed, a unique expression can be obtained for the carrier temperature T^* which is in good agreement with the measured field dependence of the ionization coefficient. In this model, a cylindrical hot carrier distribution must be assumed with the hot carrier energy in a plane perpendicular to the applied field. Exact calculations of the magneto-resistance of such a distribution can be made verifying that the drift velocity is indeed saturated.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

A hot-carrier analysis of submicrometer MOSFET's

Based on Monte Carlo (MC) device simulations, an analysis of hot-carrier effects in submicrometer n-MOSFETs is presented that provides detailed insight because the high-energy electrons are treated directly. The DC stress characteristics of both lightly-doped drain (LDD) and conventional As source/drain devices are found to correlate with the surface hot-electron concentration, and agreement with experimental data shows that the electron flux above 3 eV, integrated along the channel, can be used to predict device degradation. The simulations indicate that the whole DC stress characteristic can be attributed to hot electrons, while the holes generated by impact ionization have a very small probability of gaining enough energy to be injected over the oxide barrier     

Examination of gradual-junction p-MOS structures for hot carriercontrol using a new lifetime extraction method

The effect of junction engineering on the hot carrier lifetimes of p-MOS transistors is examined. A normalizing method for predicting lifetimes is developed and used to show that a critical parameter controlling the lifetimes of submicrometer p-MOS devices is the size of the hot-carrier-damaged region. This is verified on conventional and gradual-junction transistors, where different implant species and energies were used to alter the source and drain junction profiles. Conventional junction devices with gate currents up to 100 times larger than those of gradual junction devices were found to have the same lifetimes as gradual junctions devices for the same effective transistor length. It is concluded that, contrary to n-MOS transistors, controlling the size of the damage region is as important as, if not more important than, reducing the hot electron gate currents by junction engineering in p-MOS devices     

Hot electrons and holes in MOSFET's biased below the Si—SiO2interfacial barrier

This work presents an investigation of low-voltage hot carrier injection in submicrometer size MOSFET's showing that for both electrons and holes it can take place even when the maximum energy to be gained by the applied field is less than the Si-SiO2interfacial barrier height. In the case of electrons, it is also shown that the injection process, due to Auger recombination at low applied drain-to-source voltages (VDS), is well described by the lucky-electron model (LEM) as soon as VDSexceeds the threshold for this to become applicable.     

Evidence of substrate enhanced high-energy tails in thedistribution function of deep submicron MOSFETs by light emissionmeasurements

This letter reports direct experimental evidence that the high-energy tail of the hot carrier luminescence distribution of deep submicron silicon MOSFETs is essentially modified by the application of a substrate voltage. The bias and temperature dependence of the phenomenon are consistent with an enhancement of the high-energy tail of the energy distribution due to a second impact ionization event occurring at the drain to substrate junction     

Degradation of gain in bipolar transistors

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar h_FE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&T's 0.8 μm BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute h_FE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BV_EBO is deduced for constant voltage stress (V_stressEBO) conditions, confirming the importance of secondaries in the process of degradation     

A new approach to modeling the substrate current of pre-stressedand post-stressed MOSFET's

In this paper, we propose a closed form expression of a new and accurate analytical substrate current model for both pre-stressed and post-stressed MOSFET's. It was derived based on the concept of effective electric field, which gives a more reasonable impact ionization rate in the lucky-electron model. This effective electric field, composed by two experimentally determined parameters, can be regarded as a result of nonlocal heating effects within devices. This model shows a significant improvement to the conventional local field model. One salient feature of the present model is that it allows us to characterize the time evolution of the substrate current of stressed MOSFET's for the first time. Experimental verification for a wide variety of MOSFET's with effective channel lengths down to 0.3 μm shows that the new model is very accurate and is feasible for any kind of MOS device with different drain structures. The present model can be applied to explore the hot carrier effect in designing submicrometer MOS devices with emphasis on the design optimization of a device drain engineering issue. In addition, the present model is well suited for device reliability analysis and circuit level simulations     

Particle conservation in the hot‐carrier solar cell

In conventional p–n junction solar cells, carrier multiplication by impact ionisation, is negligible, owing to the low temperature of the electron–hole pairs. This leads to particle conservation between the net number of absorbed photons and the number of electron–hole pairs withdrawn from the cell. In hot‐carrier solar cells, in which electrons are at a high temperature by assuming suppression of electron–phonon scattering, such particle conservation leads to peculiar results. Numerical calculations show that entire current–voltage characteristics with meaningful values of temperature and chemical potential do not exist. If the energy at which electron–hole pairs are extracted is smaller than the average energy of absorbed photons, the temperature of the electrons and holes becomes much larger than the tem perature of the sun. When the extraction energy is larger than the average energy of the absorbed photons, an entire current–voltage curve cannot always be obtained. It follows that impact ionisation and Auger recombination cannot be neglected when the thermal energy of the electron–hole pairs is comparable to the bandgap of the absorber. Accounting for these processes results in current–voltage characteristics that are well behaved. Copyright © 2005 John Wiley & Sons, Ltd.     

Radiation-induced breakdown of a nonuniformly doped PN junction

A quasi-hydrodynamic model is developed for carrier transport under ionizing irradiation subject to the nonsteady-state thermal effect of the current on the semiconductor lattice. Computer simulations are run for the thermal breakdown of a nonuniformly doped pn junction caused by a pulse of ionizing radiation. The simulation model includes the temperature dependence of electron energy and momentum relaxation times and the suppression of impact ionization with increasing temperature. The simulation results are verified by comparison with previously reported experimental data.     

Time-Resolved Temperature Measurement of AlGaN/GaN Electronic Devices Using Micro-Raman Spectroscopy

We report on the development of time-resolved Raman thermography to measure transient temperatures in semiconductor devices with submicrometer spatial resolution. This new technique is illustrated for AlGaN/GaN HFETs and ungated devices grown on SiC and sapphire substrates. A temporal resolution of 200 ns is demonstrated. Temperature changes rapidly within sub-200 ns after switching the devices on or off, followed by a slower change in device temperature with a time constant of ~10 and ~140 mus for AlGaN/GaN devices grown on SiC and sapphire substrates, respectively. Heat diffusion into the device substrate is also demonstrated     

Study of MOS gate dielectric breakdown due to drain avalanche breakdown

This work reports the effects of drain impact ionization injection on the gate dielectric breakdown. Results show that due to the high energy hot carrier injection, the gate oxide can break down twice at a low oxide electric field (<1.2 MV/cm). The first breakdown occurs simultaneously with the drain avalanche breakdown whereas the second breakdown occurs beyond the drain breakdown. It is further identified that the first gate oxide breakdown is governed by the thermionic emission of hot electrons at low oxide fields (<1.0 MV/cm) and by the scattering processes at higher oxide fields. The second breakdown is attributed to the Fowler–Nordheim (F–N) tunneling.