Blue light generation in LiNbO/sub 3/ waveguide SHG device with first order domain-inverted grating formed by EB scanning

An LiNbO/sub 3/ waveguide SHG device for blue light generation by first order quasiphase-matching was fabricated using the electron-beam scanning domain inversion technique for the first time. The period of the domain-inverted grating was 3 mu m and blue light of wavelength 0.44 mu m was obtained. The normalised SHG efficiency was 70%/W.<>     

Pulsed and CW high temperature operation of InGaAs/GaAs strained layer vertical cavity surface emitting lasers

The performance of strained layer InGaAs/GaAs vertical cavity surface emitting lasers defined by ion implantation over a approximately 75 degrees C temperature range is reported on. Maximum CW output levels for the temperature extremes of 10 and 86 degrees C are 7.5 MW and 200 mu W, respectively for 20*20 mu m/sup 2 /devices. The temperature dependence of the CW threshold current exhibits exponential behaviour to 80 degrees C.<>     

Measurement of reduction in SHG coefficient of LiNbO/sub 3/ by proton exchanging

The SHG coefficient of a proton-exchanged layer of LiNbO/sub 3/, relative to the bulk value, has been measured for the first time by non-phase-matched SHG using a grating sample. It was found that the d/sub 33/ coefficient is reduced to approximately 0.5 of the bulk value by proton exchanging in pure benzoic acid.<>     

Harmonic blue light generation in periodically poled bulk near-stoichiometric MgO:LiNbO/sub 3/

A periodically poled structure with 6.95 /spl mu/m period and 10 mm interaction length was fabricated in a 1 mm-thick 1.8 mol% MgO doped near-stoichiometric LiNbO/sub 3/ (MgSLN) by using a multi-pulse poling technique. Blue SHG characteristics of this periodically poled MgSLN were investigated, in comparison with a periodically poled 5 mol% MgO doped congruent LiNbO/sub 3/.     

Optimized second-harmonic generation in quantum cascade lasers

Optimized second-harmonic generation (SHG) in quantum cascade (QC) lasers with specially designed active regions is reported. Nonlinear optical cascades of resonantly coupled intersubband transitions with giant second-order nonlinearities were integrated with each QC-laser active region. QC lasers with three-coupled quantum-well (QW) active regions showed up to 2 /spl mu/W of SHG light at 3.75 /spl mu/m wavelength at a fundamental peak power and wavelength of 1 W and 7.5 /spl mu/m, respectively. These lasers resulted in an external linear-to-nonlinear conversion efficiency of up to 1 /spl mu/W/W/sup 2/. An improved 2-QW active region design at fundamental and SHG wavelengths of 9.1 and 4.55 /spl mu/m, respectively, resulted in a 100-fold improved external linear-to-nonlinear power conversion efficiency, i.e. up to 100 /spl mu/W/W/sup 2/. Full theoretical treatment of nonlinear light generation in QC lasers is given, and excellent agreement with the experimental results is obtained. For the best structure, a second-order nonlinear susceptibility of 4.7/spl times/10/sup -5/ esu (2/spl times/10/sup 4/pm/V) is calculated, about two orders of magnitude above conventional nonlinear optical materials and bulk III-V semiconductors.     

Continuous-wave erbium-diffused LiNbO/sub 3/ waveguide laser

The first integrated optical laser in LiNbO/sub 3/, doped by an indiffusion of Er/sup 3+/ prior to channel-guide fabrication by Ti diffusion is reported. Pumped by a colour centre ( lambda /sub p/=1.477 mu m), CW operation at lambda =1.532 mu m ( Delta lambda approximately 0.3 nm) with a threshold of approximately 8 mW absorbed power was achieved.<>     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

Optical characterization of ion implantation in Si and Si/SiO2 structures: spectroellipsometric (SE) and second harmonic generation (SHG) results

This paper presents results concerning the ability of second harmonic generation (SHG) and spectroellipsometry (SE) to probe ion implantation effects in Si and Si/SiO₂ structures. BF₂ and As implanted Si/SiO₂ (0.1 μ) samples are analysed by SHG; both dose and ion type effects are identified and the SHG signals are correlated with simulations of ion and vacancies depth distributions. Boron implanted Si samples were investigated by SE, showing how important information about the re-growth of the Si network after post-implantation annealing can be obtained. The multilayer model approach which was used for the data analysis can give also details referring to the thickness of the oxide, on low resistivity substrates. These results are also supported by computer simulations.     

Single transverse-mode filtering utilizing ion implantation: application to 1.48-/spl mu/m unstable-cavity lasers

We demonstrate the relevance of ion implantation of the multiple quantum-well active layer in unstable-cavity lasers as a means of efficiently filtering the parasitic higher order waves by introducing additional propagation loss within the cavity. Several H/sup +/ implantation schemes are proposed and a comparison is successfully made of experiment to a beam propagation method (BPM) model on the basis of modal behavior. The work finally resulted in improved single transverse-mode behavior of those lasers: more than 1.3 W CW of diffraction-limited power at 1.48 /spl mu/m was then obtained utilizing a two-step implantation process.     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.     

High-performance and low-cost 0.15-/spl mu/m nMOSFETs using simultaneous N-gate and source/drain doping process

A fabrication method for high performance and low cost nMOSFETs suitable for 0.15 and sub-0.15 /spl mu/m CMOS technology is proposed. In this method, n-poly gate doping prior to the definition of gate poly was skipped, i.e., gate poly is simultaneously doped by the source/drain ion implantation. Then, the source/drain implantation dose was increased by the amount used for gate pre-doping process. Although gate pre-doping is skipped, device performances such as device on-off current characteristics, active and poly sheet resistance and junction leakage current are compatible to the pre-doping ones. Moreover, the proposed method has the advantages of low cost and high yield because one mask step and several processes are reduced. The degree of active damage by the doubled source/drain implantation dose was investigated using the transmission electron microscopy, and high resolution x-ray diffraction spectroscopy.     

Low-threshold proton-implanted 1.3-/spl mu/m vertical-cavity top-surface-emitting lasers with dielectric and wafer-bonded GaAs-AlAs Bragg mirrors

We demonstrate a new structure for long-wavelength (1.3-/spl mu/m) vertical-cavity top-surface-emitting lasers using proton implantation for current confinement. Wafer bonded GaAs-AlAs Bragg mirrors and dielectric mirrors are used for bottom and top mirrors, respectively. The gain medium of the lasers consists of nine strain-compensated AlGaInAs quantum wells. A record low room temperature pulsed threshold current density of 1.13 kA/cm/sup 2/ has been achieved for 15-/spl mu/m diameter devices with a threshold current of 2 mA. The side-mode-suppression-ratio is greater than 35 dB.     

Efficient improvement of hot carrier-induced degradation for 0.1-/spl mu/m indium-halo nMOSFET

The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-/spl mu/m nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900/spl deg/C) for a longer time.     

Bolometric YBa/sub 2/Cu/sub 3/O/sub 7-x/ infra-red detector

Results of the measurement of optical detection in YBa/sub 2/Cu/sub 3/O/sub 7-x/ superconducting epitaxial films at a wavelength of 0.94 mu m are presented. These films show bolometric responses at temperatures in the resistive transition regions which are strongly dependent on the bias current. For 0.94 mu m radiation, electronically chopped at 20 Hz, measurement of a meander bridge yields a bolometric responsivity of approximately 6.1 V/W.<>     

利用二次谐波产生研究Al2O3/Al(111)表面的动力学变化

主要介绍了当激光入射到单晶金属Al2O3／Al(111)表面时将发生二次谐波产生(SHG)现象的实验装置和实验方法,利用该装置可以研究SHG和从Al2O3／Al(111)表面反射的SHG在空间各向异性的变化情况,从而可以探测Al2O3／Al(111)表面结构对称性。实验中发现,当脉冲激光功率在2×106 W／cm2-9．6×106W／cm2范围内变化时,没有检测到SHG信号的各向异性变化;当使用P-极化泵浦激光时,发现Al2O3／Al(111)样品绕法线旋转360度时,P-极化的SHG信号在空间三个方向上呈现最大值相等;当使用脉冲强度为12×100 W／cm2的1064 nm P-极化泵浦激光时, Al2O3／Al(111)表面被损坏,损坏后的表面其SHG信号并不呈现对称的各向异性变化,当使用脉冲强度为11×106W／cm2的1064 nm P-极化泵浦激光时产生表面退火现象,从退火表面所产生的反射532 nm P-极化SHG信号中发现,SHG信号呈现衰减的各向异性成分。     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

Impact of the S/D extension doping profile on the /spl Psi/-cell concept

The viability of the /spl Psi/-cell concept that has been proposed for CMOS embedded flash applications is examined as the CMOS dimensions shrink down. More specifically, we focus on the dependence of the memory operation on the doping profile underneath the spacer. We show that for optimum operation of the /spl Psi/-cell concept below 0.18 /spl mu/m CMOS technologies, the S/D extension implantation process step should be omitted.     

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-/spl mu/m single-gate low-power SRAM device

A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-/spl mu/m single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology.     

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-/spl mu/m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I/sub t2/) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.     

GaAs/GaAlAs asymmetric Mach-Zehnder demultiplexer with reduced polarization dependence

A two-channel GaAs/AlGaAs asymmetric Mach-Zehnder wavelength demultiplexer with reduced polarization dependence was demonstrated. The device was fabricated on a single heterostructure comprising a 1.45- mu m-thick layer of GaAs on a 6.0- mu m-thick Ga/sub 0.85/Al/sub 0.15/As buffer layer. The epitaxial layers were grown by MOCVD (metalorganic chemical vapor deposition) on an n/sup +/ GaAs substrate. The single-mode rib waveguides, 3 mu m wide and 0.29 mu m high, were fabricated using standard photolithographic techniques followed by chemical etch and removal of the resist mask. Extinction ratios of 24.1 dB for transverse electric (TE) and 22.5 dB for transverse magnetic (TM) polarized light were measured on a device with an anti-reflection coating on its input and output facets. The active length of the device is approximately 6.5 mm and total loss of 1.1 dB was obtained in a 16-mm-long chip.<>