Ferroelectric Non-Volatile Logic Devices

Ferroelectric non-volatile logic is proposed. It is low power and can be used for dynamic reconfigurable logic technologies by storing logic state or circuit configuration non-volatility. Cost of LSIs can be decreased by switching circuit blocks. The fundamental device of non-volatile latch was developed and characterized. Moreover, advanced functional device that can do operation at a ferroelectric capacitor was also fabricated. The durability and the low power consumption were confirmed.     

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.     

Plasma Etch Processes for Embedded FRAM Integration

We describe the etch processes used for integration of embedded ferroelectric random access memory (FRAM) within a standard CMOS logic flow. The ferroelectric module is inserted following front-end contact formation and prior to backend integration using only two additional mask levels: capacitor pattern and bi-level via pattern. The single-mask stack etch process employs a TiAlN hardmask to define Ir/IrO_x/PZT/IrO_x/Ir capacitors. Protective sidewalls can be formed using an etchback process. The bi-level via etch and subsequent metal fill processes complete the FRAM module formation. Functional 4 MB arrays embedded with 5 levels of Cu/FSG integration have been demonstrated.     

Ferroelectric nonvolatile logic

Abstract

This paper describes the design of nonvolatile logic elements using ferroelectric materials. Two separate approaches are discussed. The first approach involves shadowing a CMOS latch or flip-flop with a single bit 2T/2C ferroelectric memory. The second approach offers improved density by integrating ferroelectric capacitors within the logic element. Both designs employ non-switching ferroelectric capacitors to establish the optimum bit line load in the absence of sufficient parasitic capacitance. The paper further describes low-voltage and wide-voltage design techniques used to realize 2.7 – 5.5V products on a “5-volt” ferroelectric process. These same techniques allow 1.8V ferroelectric memory products to be designed using the upcoming generation of production ready “3-volt” ferroelectric materials. Layout effects are discussed, as well as bit/cell ratio optimization.     

DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT

Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.     

A new scalable and reconfigurable architecture

As optical link speeds get faster, demands for performance and embedded network services impose increasing flexibility demands. Internet routers must become more efficient and programmable. A new hardware architecture using a dynamic reconfigurable logic (DRL) circuit, along with its design methodology, is proposed. Our approach is to allocate all resources using the dynamic reconfigurable control switch (DRCS). The design space for scheduling the DRL for the networking application (router) is explored. Our proposal outperforms recent network processors since it has a better memory interface and because chained nodes of a thread can be executed at once. Our architecture offers an attractive alternative to expensive commercial solutions employing multiple content addressable memory (CAM) devices and application specific integrated circuits (ASICs). By providing high-performance at low per-ports costs, our architecture is a prime candidate for system-on-chip (SoC) solutions for next generation programmable router port processors.     

Key Technologies for High Density FeRAM Applications

Ferroelectric random access memories (FeRAMs) are new types of memory devices especially suitable for mobile applications due to their unique properties such as non-volatility, small cell size especially with chain cell design, fast read and write as well as low voltage / low power behavior. Although standard CMOS processes can be used for frontend processes, FeRAM technology development has to overcome major challenges due to new materials used for capacitor formation. In this paper the advantages and disadvantages of different ferroelectric materials, especially in terms of low thermal budget for crystallization and capacitor formation, are discussed. In addition, major development issues for high-density applications like different capacitor encapsulation concepts to protect the capacitor form backend process damage and degradation by hydrogen are presented. Results from a recently developed 1T / 1C 8Mb FeRAM are discussed. The FeRAM is based on a 0.25 w m CMOS process. Due to the chain cell architecture a chip size of 76mm 2 was achieved using 2 metal layers.     

A 1.8 V 4 k FeRAM Chip Using 0.2 u Process and Novel Design Techniques

Due to the increasing demand for high speed, low voltage or low power applications, non-volatile memory becomes even more important and more challenging as technology advances. With ferroelectric memories, which provides fast write and fast read with relatively low power, the challenge is to provide a ferroelectric random access memory (FeRAM) chip that operates at low voltages with the smallest geometry available in the technology. In this paper, we present a 1.8 V 4 k bit ferroelectric memory chip design, with emphasis on core/core control, bit:cell determination and key circuit design as well as simulation results based on a 0.2 u CMOS double level metal process and ferroelectric process parameter assumptions.     

Ferroelectric polymer Langmuir-Blodgett films for nonvolatile memory applications

We review the potential for integrating ferroelectric polymer Langmuir-Blodgett (LB) films with semiconductor technology to produce nonvolatile ferroelectric random-access memory (NV-FRAM or NV-FeRAM) and data-storage devices. The prototype material is a copolymer consisting of 70% vinylidene fluoride (VDF) and 30% trifluoroethylene (TrFE), or P(VDF-TrFE 70:30). Recent work with LB films and more conventional solvent-formed films shows that the VDF copolymers are promising materials for nonvolatile memory applications. The prototype device is the metal-ferroelectric-insulator-semiconductor (MFIS) capacitance memory. Field-effect transistor (FET)-based devices are also discussed. The LB films afford devices with low-voltage operation, but there are two important technical hurdles that must be surmounted. First, an appropriate method must be found to control switching dynamics in the LB copolymer films. Second, the LB technology must be scaled up and incorporated into the semiconductor-manufacturing process, but since there is no precedent for mass production of LB films, it is difficult to project how long this will take.     

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90‐nm CMOS standard technology show that the proposed logic improves the average power‐delay product by about 40% for the attempted benchmarks.     

QCA技术在递归盒式滤波器中的应用

量子点元胞自动机(quantum dot-cellular automata, QCA)因其延迟时间短、功耗低以及占用面积小等优点被当作代替CMOS的新型技术之一。针对CMOS器件尺寸日益减小导致的高功耗和电容寄生及串扰问题,本文首次利用QCA技术构建了一种递归盒式滤波器。其中,提出了一种全新的QCA全加器,较已提出的QCA全加器减少了55%的电路面积;少使用了56.7%的元胞数;量子成本也降低了10%以上。并以此为基础设计了一种高效的行波进位加法器(ripple carry adder, RCA)以及一种高效的进位选择加法器(carry select adder, CSA)来构成盒式滤波器的加法单元。以此构建的盒式滤波器较一般QCA盒式滤波器节省了32.6%的硬件资源;减少20%的电路运行时间;减少了48.7%的功耗。并使用QCA Designer仿真,结果表明,本设计完全可以代替实现传统的盒式滤波器功能,并在效率、功耗、电路面积、资源占用方面均有显著降低。     

Design of a reversible structure for memory in quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) technology has limitations in reducing the area and size of circuits. The disadvantages of this technology include high power consumption and temperature problems. Quantum-dot cellular automata (QCA) is a new technology that can overcome these shortcomings. Reversible logic is technology used to reduce the power loss in QCA. QCA can be used to design memories that require high operating speed. In this paper, we propose a structure for the reversible memory in QCA. The proposed structure utilizes three-layer technology, which has a significant impact on circuit size reduction. The proposed structure for the reversible memory has 63% improvement in cell number, a 75% improvement in area occupancy, and a 60% reduction in delay compared to the previous best structure.     

Circuits simulation of switch devices furnished with gain cell combined to FeRAM

Abstract

This paper has described a new concept on programmable switch device furnished with gain cell combined to FeRAM. Compared with memories but ferroelectric memories under many aspects, they have even been favorably labeled the ideal memory because of their non-volatility, ease of programming and operation by low voltage. As the programming switch, which is very attractive for logic application, SRAM, anti-fuse, flash type devices are well known. They have been required that satisfy non-volatility and low-voltage programming simultaneously. Some structures with ferroelectric material have been proposed and studied as solution of these problems. However, it seemed hard that these type devices are realized now from a viewpoint of fabrication process and low voltage operation. Therefore, we propose a new switch device furnished with gain cell combined to FeRAM. We have studied and simulated this switch device by SPICE. This basic circuit is composed of two blocks. One is switching block that includes gain cell, and the other is memory block that is FeRAM. Circuits, which we designed, amplify bit line's voltage up to Vdd or ground at sense amplification according to FeRAM data. The bit line voltage determines the logic state for gate electrode of switch transistor. The way to read is destructive read out. However, we can transfer information of bit line voltage during plate line is low-level voltage. The way to write FeRAM is similar to conventional way. It is revealed that the basic circuit with FeRAM connected gain cell could work correctly in simulation. In addition, this kind of device is hopeful of many logic applications.     

Multiple-valued logic

The ultimate usefulness of a number system depends on its implementation. Multiple-valued logic has been implemented in charge-coupled devices (CCD). In this technology, logic values are encoded as charge. For example, prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland). Hitachi has implemented a 16-valued memory that stores the equivalent of 10⁶ bits. CCD is more compact than any other VLSI technology. Although it is slower than CMOS (complementary metal oxide semiconductor), it is much faster than the disk and has the potential of replacing the disk. The use of multiple-valued logic in CCD increases its storage capacity significantly. Multiple-valued logic has also been implemented in current-mode CMOS     

Effects of UV process on high density 1T1C fram device

Abstract

A ultraviolet (UV) process is commonly used in fabricating memory devices such as DRAM and SRAM without degrading the memory properties. However, in high density FRAM, the effect of UV light on ferroelectric properties has never been confirmed in real functional FRAM devices FRAM. Therefore, in this paper, we investigated the UV effect on ferroelectric properties and established an optimal back-end process for 1T1C 4Mb FRAM. It was found that the UV light illumination has strong influence on the hysteresis loop of ferroelectric capacitors. The polarization of the capacitor decreased and coercive voltage shifted after exposure to the UV light. It might be attributed to the fact that UV light generates free space charges in the ferroelectric layer and these charges are trapped at the electrode/ ferroelctric interface of the ferroelectric capacitor.     

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFETs in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The devices were only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The designs consist of a small array of logic gates. Other gates could easily be produced. They are linked by FFETs that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.     

高帧频DVI接口彩色CMOS数字相机系统设计

针对高帧频彩色CMOS图像传感器在机器视觉高速成像领域中的应用,本文介绍利用高性能可编程逻辑器件FPGA实现CMOS图像传感器MI-MV13的高速驱动时序的设计,并且在FPGA内部设计了高速FIFO缓存器和双口RAM来完成Bayer彩色阵列图像数据的实时同步转换输出RGB彩色分量。最终由2片专用DVI接口集成芯片SiI178实现了DVI-IDualLink模式的高帧频高分辨率彩色图像输出,DVI接口方便显示终端和高速存储设备链接。该相机系统具有集成度高、低功耗、接口通用紧凑、传输带宽高的优点。     

Process Integration of Embedded FeRAMs

This paper describes the general aspects of embedding Ferroelectric Memories (FeRAMs) with logic circuits and/or microcontrollers. These devices and stand-alone memories constitute the main thrust of applications of ferroelectric memories. The problems associated with embedding test the robustness and compatibility of the FeRAM process with established CMOS integrated circuits. As integrated circuits technology advances in lithography, FeRAMs meet the challenge, but new problems appear. In this review, existing embedded FeRAMs of the 0.8/0.6 generation will be discussed. A program for the 0.35/0.25 generation, and the 0.18 challenges are outlined and addressed. The paper also reviews the application of FeRAM Smart Cards. This application is becoming the best example of embedded FeRAMs in which to demonstrate the System-One-Chip technology direction. Smart Card ICs clearly take advantage of the low power, high-write speed and long endurance characteristics of Ferroelectric Memories.     

The Effects of Integration Processes on Properties of One Transistor MFMPOS Memory Devices

Integration processing of one-transistor memory devices deals with the following issues: film quality of ferroelectric materials, integration process induced damages such as etching and forming gas annealing damage of ferroelectric materials, the alignment for devices. In order to make high quality one-transistor memory devices, integration processes including nitride gate replacement, oxide trench etching structures, selective deposition, etc. have been investigated for fabrication of one transistor MFMPOS (M: Metal, F: Ferroelectrics, M: Metal, P: polysilicon, O: oxide, S: silicon) memory devices. The integration processes for one transistor memory device have also been optimized to reduce process-induced damages. Based on the experimental results, MOCVD selective deposition can make higher quality patterned ferroelectric thin films, damascene structure with CMP processes can reduce the etching damages. Therefore, the high quality one transistor MFMPOS memory devices have been made.     

不应再搞拉闸限电

我国以往采用的拉闸限电,原是对付缺电而采取的一种应急措施,是一种不正常操作。可是,由于过去缺电延续的时间过长,拉闸限电过于频繁采用,竟逐渐演变为“正常”操作。随着我国改革开放的不断发展,拉闸限电所造成的物质损失和精神创伤将越来越严重,今后不再存在拉闸限电的社会空间,决不应再搞拉闸限电。