Complementary current-mirror logic

A logic family which operates primarily on current rather than voltage levels is proposed. This family can perform with the high speed of emitter-coupled logic (ECL), and so is a suitable candidate for mainframe computer use. In addition, the inherent gate power dissipation in the absence of an input signal resembles CMOS, making large-scale integration a possibility. Simulated results using 12-GHz n-p-n and 1.2-GHz p-n-p devices show that 120-ps gate delay is possible at a 1-mW power level. The performance of a basic logic cell and ways of forming several types of logic circuits are discussed. Line-driving capability is compared with ECL, and in many situations it is found to compare very favorably in terms of energy requirements as well as line-to-line noise coupling. The potential for multilevel applications is briefly discussed     

STS-768 multiplexer with full-rate output data retimer in InP HBT

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.     

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic

A new planar high-density (10/sup -3/ mm/sup 2//gate) GaAs IC technology has been used for fabricating MSI digital circuits containing up to 75 gates/chip. These digital circuits have potential application for gigabit microwave data transmission and processor systems. The circuits consist of Schottky diode FET logic NOR gates, which have provided propagation delays in the 75-200-ps range with dynamic switching energies as low as 27 fJ/gate on ring oscillator structures. Power dissipation levels are compatible with future LSI/VLSI extensions. Operation of D flip-flops (DFF) as binary ripple dividers (/spl divide/2-/spl divide/8) was achieved at 1.9-GHz clock rates, and an 8:1 full-data multiplexer and 1:8 data demultiplexer were demonstrated at 1.1-GHz clock rates. This corresponds to equivalent propagation delays in the 100-175-ps range for these MSI circuits. Finally, a 3x3 parallel multiplier containing 75 gates functioned with a propagation delay of 172 ps/gate and with average gate power dissipations of as low as 0.42 mW/gate.     

67-GHz static frequency divider using 0.2-μm self-aligned SiGeHBTs

A 67-GHz 1/4 static frequency divider using 0.2-μm self-aligned selective-epitaxial-growth SiGe heterojunction bipolar transistors, with a 122-GHz cutoff frequency, a 163-GHz maximum oscillation frequency, and an average emitter coupled logic gate delay time of 5.65 ps, was developed. The pretracking master-slave toggle flip-flop (MS-TFF) of the divider increases the maximum operating frequency to about 15% higher than that of a conventional MS-TFF, yet the power consumption of the divider is 175 mW, which is 1/5 that of comparable dividers, at a supply voltage of -5.2 V     

GaAs ultra-high-frequency dividers with advanced SAINT FET's

The circuit design, fabrication, and performance of ultra-high-frequency dividers with buffer FET logic (BFL) circuits are described. Using air-bridge technology and a new, self-aligned-gate, GaAs FET process, called advanced SAINT, which avoids excess gate metal overlap on the dielectric film, 10.6-GHz operation at 258 mW is achieved. This performance is made possible by a reduction of gate and interconnection parasitic capacitance. Furthermore, the possibility of operation above 20 GHz for GaAs MESFET frequency dividers is predicted on the basis of circuit optimization and FET improvements including parasitic capacitance reduction and transconductance enhancement.     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.     

Simulations of HEMT DC drain current and 1 to 50 GHzS-parameters as a function of gate bias

The usefulness over an extended range of a high-electron-mobility transistor (HEMT) model previously validated for a 1-25-GHz S-parameter model is shown. Experimental and simulation results for the DC drain current and 1-50-GHz S-parameters of a pseudomorphic 0.32-μm gate AlGaAs-InGaAs-GaAs HEMT are presented. The model predicts the device's DC current and S-parameters as functions of the applied gate bias with good accuracy. The core of the model is directly dependent on the HEMT wafer structure and the physical gate length. As part of the modeling procedure, a value of (1.77±0.07)×10⁵ m-s^-1 is found, confirming the results of other research, for the electron velocity in undoped pseudomorphic In_0.15Ga_0.85As under ≈0.3-μm gates     

Direct measurement of picosecond propagation delays in individual logic gates by a differential optoelectronic technique

We describe the first direct measurement of single-gate propagation delays in gigabit GaAs digital IC's. Our technique uses picosecond light pulses to generate short on-chip logic-level-switched pulses and infers single logic gate delays by differential measurement of output waveforms. In the ∼ 2-GHz clock-rate D-flip-flop selected for these measurements, single-gate propagation delays of ∼ 100 ps were measured in specific NOR gates internal to the flip-flop (FF) with this new measurement technique; the technique is easily extendible to measurement of gate delays of the order of a few picoseconds.     

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak$f_T$(approx. 0.3$hbox mA/muhbox m$), peak$f_ MAX$(approx. 0.2$hbox mA/muhbox m$), and optimum noise figure$ NF_ MIN$(approx. 0.15$hbox mA/muhbox m$) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40–80 Gb/s wireline transceivers.     

VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors

Using a standard logic process, 0.13-/spl mu/m RF CMOS devices with multifinger gate structure have been fabricated. The flicker noise and minimum noise figure characteristics have been investigated with different gate layout splits, where the device parasitic resistance is the determining factor in this issue. The stripe-shaped gate configuration demonstrates better noise performance, due to the reduction of device gate resistance. In addition, the MOS varactors designed with different gate layouts were used in a 5.2-GHz voltage-controlled oscillator (VCO) design, where the VCO with the stripe-shaped (2 /spl mu/m /spl times/ 36 fingers) gate varactor improved about 6 dB in phase-noise performance at 100-kHz offset frequency than that of square-shaped (8 /spl mu/m /spl times/ 9 fingers) gate varactor.     

Optimization of GaAs power MESFET device and material parameters for 15-GHz operation

The results of recent 15-GHz measurements on GaAs power FET's are described. The microwave performance has been determined as a function of epitaxial doping level and thickness, gate recess depth, gate finger width, and source-drain spacing. The optimum values of these parameters for 15-GHz operation are epitaxial doping level approximately 1.6 × 10¹⁷cm^-3, saturated drain current with zero gate voltage in the range 330- to 400-mA/mm gatewidth, gate recess depth between 500 and 1000 Å, gate finger width ≤ 150 µm, and source-drain spacing approximately 5 µm.     

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.     

A 5-mA 1-GHz GaAs dual-modulus prescalar IC

A 1-GHz GaAs dual-modulus divide-by-128/129 prescalar IC with current drain of only 5 mA has been developed. Its current drain is one-sixth that of commercially available Si bipolar ICs used in 800-MHz band mobile radio systems. Five-level series gate low-power source-coupled FET logic (LSCFL) and the 0.50-/spl mu/m gate buried P-layer SAINT (BP-SAINT) process technology have been used to achieve this small current drain together with high-speed operation. A high-speed divide-by-4/5 modulus divider (3.1 GHz, 13 mA) and divide-by-32 divider (6.1 GHz, 19 mA) has also been designed and fabricated. These prescalars are suitable for use as synthesizers in mobile communication systems.     

A high-performance BICMOS Technology with double-polysilicon self-aligned bipolar devices

A high-performance BICMOS technology is described which incorporates 12-GHz double-polysilicon self-aligned bipolar, fully salicided CMOS devices and 1-µm features. This process is applied to a new BICMOS gate design, called transistor feedback logic (TFL), to fabricate a divide-by-16 frequency divider with a maximum operating frequency of 364 MHz. Availability of uncompromised MOS and bipolar transistors allows a free mix of pure CMOS, pure bipolar, or BICMOS gates on the same chip.     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

60-GHz power performance of ion-implantedInxGa(1-x/)AsGaAs MESFETs

State-of-the-art 60-GHz power performance is reported for ion-implanted InGaAs/GaAs MESFETs with 0.25×200-μm gate length. At output power of 100 mW, a power-added efficiency of 15% and associated gain of 4.2 dB were obtained and a saturated output power of 121 mW was achieved for the same device. These results are comparable to the best reported millimeter-wave power performance of InGaAs/GaAs pseudomorphic HEMTs     

A Short-Channel SOI RF Power LDMOS Technology With$hboxTiSi_2$Salicide on Dual Sidewalls With Cutoff Frequency$f_T sim hbox19.3 hboxGHz$

In this letter, a CMOS-compatible silicon-on-insulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi₂ salicide with SiO₂/Si₃N₄ dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 mum. For the shortest 0.25-mum gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications     

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).