A Si-bipolar technology for optical fiber transmission rates above10 Gb/s

A multiplexer operating at up to 12 Gb/s has been demonstrated using a simple, but optimized, silicon bipolar technology with 2 μm lithography. Using this simple but optimized technology, a 12 Gb/s multiplexer was implemented. Circuit simulations predict the increase of the bit rate up to at least 15 Gb/s by changing to the 1.5 μm lithography. The results of experimental investigations and circuit simulations show that low-cost silicon-based bipolar circuits will be available for future optical-fiber transmission systems with data rates higher than 10 Gb/s     

GaAs MESFET logic with 4-GHz clock rate

Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.     

Ultrahigh-speed heterojunction bipolar transistormultiplexer/demultiplexer ICs

High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively     

11.4 Gbit/s silicon bipolar multiplexer IC employing 2 mu m lithography transistors

A very high-speed 2:1 multiplexer IC operating up to 11.4 Gbit/s has been implemented. The circuit was fabricated using a 12 GHz non-polysilicon-emitter self-aligning bipolar process with 2 mu m lithography. Despite realisation in a relatively simple technology, this is the highest operating speed yet achieved with any technology.<>     

High-speed modulation of an electrooptic directional coupler

A LiNbO3:Ti directional coupler driven by an RF signal has been tested at 1.06 μm over a large modulation bandwidth. An analytical model has been developed leading to simple usable expressions to describe the theoretical dependence of the frequency spectrum of sinusoidally modulated light. The frequency response has been measured with a scanning Fabry-Perot and also with a high-speed photodiode. Both methods provided results which are in good agreement. The 9 mm long switch exhibited a 2.5 GHz bandwidth; a 16 dB extinction ratio has been achieved with a driving power of approximately 50μW/MHz. The confirmation of practical modulation response expressions shows the advantage of the optical spectrum observation, which is a very simple measurement method without any bandwidth limitation. In addition, this method has the advantage of remaining quite accurate even for large modulation signals.     

Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs

A 2:1 multiplexer (MUX) and low power selector ICs have been successfully designed and manufactured using an InP/InGaAs DHBT technology. The 2:1 MUX has been tested at data rates up to 80 Gbit/s with an output swing of 600 mV, while the selector IC has achieved operation speed up to 90 Gbit/s at a power consumption of only 385 mW.     

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.     

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s.     

An STS-N byte-interleaving multiplexer/scrambler anddemultiplexer/descrambler architecture and its experimental OC-48implementation

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies     

Sub-ft gain resonance of InP/InGaAs-HBTs

Advanced npn-InP/InGaAs HBTs are often operated at high current levels for optimum high-speed performance. Because of velocity modulation effects, these transistors may operate in base-pushout although measurements of the cut-off frequency f_t indicate the opposite. We show that the low mobility of the holes has a strong effect on the transistor operation in this regime, which is only revealed from a dynamic analysis: The unilateral power gain peaks far below f_t followed by a -40 dB/dec roll-off. The effect was thoroughly analyzed and as a result, we present a simple equivalent circuit model that successfully describes transistors operating in pushout up to very high frequencies     

A 60-GHz fT super self-aligned selectively grownSiGe-base (SSSB) bipolar transistor with trench isolation fabricated onSOI substrate and its application to 20-Gb/s optical transmitterICs

A 60-GHz cutoff frequency (f_T) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C_CS. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-μm wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f_T and the maximum frequency of oscillation f_max were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s     

A ring oscillator based frequency synthesizer without using frequency divider

A novel indirect frequency synthesizer (FS) circuit comprising a multiplexer (MUX) controlled ring oscillator (RO) and a Hogge phase detector has been proposed. The circuit will synthesize signals having better spectral purity and will consume less power compared to conventional indirect FS circuits. The MUX controlled RO will provide higher flexibility in frequency control and the voltage controlled oscillator (VCO) sensitivity can be varied easily to keep loop gain fixed for different values of synthesized signal frequencies. Hardware experimental results have been given to establish theoretical anticipations.     

A 20 GHz 8 bit multiplexer IC implemented with 0.5 μm WNx/W-gate GaAs MESFET's

An ultrahigh-speed 8 bit multiplexer (MUX) has been developed for future-generation optical-fiber communication systems having a data rate of 20 Gb/s. This IC was fabricated using a 0.5 μm WN_x/W-gate GaAs MESFET process based on optical lithography, ion implantation, and furnace annealing for good reproducibility and high throughput. The WN_x/W bilayer gate has a low sheet resistance, improving the circuit high frequency performance. To attain 20 GHz operation, advanced circuit techniques for the source-coupled FET logic (SCFL) were introduced. A cross coupled source-follower (CCSF) was developed mainly for the highest speed buffers to enhance the bandwidth. The first-stage T-type flip-flop was designed with optimization techniques and operated up to 21.1 GHz     

Attenuation statistics in Italy as measured by the SIRIO satellite during its five year lifetime

The results of a campaign of attenuation measurements carried out by means of the Italian satellite SIRIO at the two frequencies 11.6 and 17.8 GHz are presented. The campaign lasted five years (1978- 1982) and yielded almost continuous measurements at the lower frequency (acquired in three Italian stations) and measurements for a considerable fraction of time at the higher one (acquired in two of the three stations). The major aim of these measurements was to acquire long-term statistics to be employed in future earth-space radiolink design. This objective has been fully accomplished, owing to the very long life of the satellite, and the acquired data have been already utilized, properly extrapolated in frequency, for designing the domestic satellite system Italsat planned to start in 1987. Year-to-year and site-to-site variation have been found to be very high. Conversely the ratio between equiprobable values of attenuation at the two frequencies has proved to be very similar in the two stations and rather stable across the attenuation range.     

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mWbit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

This paper reports the first CMOS implementation of an 8:1 byte-interleaved multiplexer (byte-MUX) operating in the Gb/s region, together with an 8:1 bit-interleaved multiplexer (bit-MUX). A future generation 0.15-μm CMOS technology has been applied. Both chips use identical bit-MUX cores with a static shift-register architecture, and have ECL interfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW/GHz dependence on clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with a power dissipation of 118 mW. This revel of performance has been achieved by a novel row-column exchanger configuration, critical path reduction and precise clocking techniques utilized in the bit-MUX core, and the development of high-speed I/O buffers     

Noise of field-effect transistors at very high frequencies

The minimum noise factor of a field-effect transistor has been computed at high frequencies on the basis of the thermal noise of the real parts of the equivalent circuit. A treatment of the intrinsic FET is followed by a consideration of the influence of feedback, parasitic output impedance and parasitic impedance in series with the source on the noise factor. Moreover, the difference between common-gate and common-source configuration has been considered. For frequencies smaller than the gain-bandwidth product fgbthe factorF_{min} - 1varies linearly with the frequency, whereas at higher frequencies this factor varies with f². The computed results are compared with measurements on both JFETs and MOSFETs in the frequency range 100-1500 MHz at different conditions of operation. The agreement is rather good. For the JFET the value ofF_{min}(f_{gb}) approx 2.5; for the MOSFET somewhat higher values are found due to the presence of substrate depletion effects.     

A 1.2 GHz frequency synthesizer using a custom-design divide-by-20/21/22/23/24 GaAs circuit

The authors describe the circuit design and the process utilized to fabricate a 1.2 GHz 380-mW divide-by-20/21/22/23/24 GaAs circuit aimed at frequency synthesizer applications. The circuit consists of a 5/6 prescaler, a divide-by-4 circuit, and a four-channel multiplexer. The circuit has been implemented with BFL gates fabricated with 0.7-/spl mu/m planar self-aligned normally-on MESFETs. Further improvement can be expected by utilizing DCFL gates instead. A maximum frequency of 2.5 GHz and an internal active power of 50 mW have been simulated. Consequently the normally-off (N-OFF) GaAs circuit would exhibit a speed by power product four times lower than that of equivalent Si ECL dividers based in bipolar processes being developed today.     

Parallel-path digital-to-analog converters for Nyquist signal generation

Nyquist-rate digital-to-analog converters (DACs) can generate frequencies up to half the sampling frequency. It is, however, impractical to generate such high frequencies. Due to its nature, the converter will not only generate the desired signal itself but also, often undesired, image frequencies. For frequencies near the Nyquist frequency, an image with almost exactly the same amplitude appears very close to the signal. An extremely steep filter is required. Therefore, real-life systems do provide oversampling to locate the Nyquist image further away from the wanted signal. In practice, the signal frequency has to be reduced if the maximum sampling rate is reached. We propose a technique that conversely removes this Nyquist image so that only further away Nyquist images with lower amplitudes have to be filtered off. The proposed technique is applied to the design of a dual 6-bit binary current-steering DAC running at 250 MS/s.     

Experimental proof-of-principle results on a mode-selective inputcoupler for gyrotron applications

Proof-of-principle results for a mode selective input coupler are presented. Transmission and reflection measurements for the TE₀₂ cylindrical waveguide mode are given along with the output mode pattern. The results show good agreement for the cutoff frequency, mode pattern general behavior and variation with frequency for signals above cutoff. A maximum passband of 1.2 GHz (~7%) has been achieved. Comparisons with theory for overall frequency response (from 15 to 18 GHz) and mode pattern characteristics (at 17.5 GHz) are also presented. The design and concept are promising for harmonic gyrotron-traveling-wave-tube amplifier and phase-locked gyrotron oscillator applications     

Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz

It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz.