Numerical analysis of MOS magnetic field sensors

A new method of numerical analysis of MOS magnetic field sensors is described, which is based on a lumped discrete approach and the application of a general-purpose circuit-analysis program. The channel region of the device is represented by a network of identical L-type circuit cells. A cell consists exclusively of conventional MOS devices, independent voltage sources and controlled current sources, while the magnetic field appears as a parameter in some of these devices. The method allows for an accurate two-dimensional numerical analysis of MOS sensors, including effects which have been neglected hitherto, such as transverse current flow and nonuniform charge density across the channel. Numerical results are given for conventional MOS plates, split-drain MOS devices and distributed current source biased MOS Hall plates.     

模电教学中BJT与MOS的近似性分析

BJT 与MOS器件及电路是模电重要内容；教学中二者的电路模型与分析方法不一致，学生困惑于两套不同的器件及电路知识。本文在遵循器件及电路工作原理的基础上，首次将二者在小信号模型、电路参数、I-V方程、特性曲线、工作区间、指标计算上进行完整的近似性分析及一致性推导；在二者电路计算中，用三种单管单级放大器实例，阐述近似分析方法的便利性。本文是模电教学的有力补充。     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

MOS IC crosspoint switch for space division digital switching networks

An MOS IC crosspoint switch for space division digital switching network is described. A sense amplifier for compensation of signal attenuation through the MOS IC switch is also considered. Transmission of a 50-100 Mbit/s bit rate digital signal seems a reasonable design objective on the basis of analysis of a preliminarily fabricated MOS IC switch and the design characteristics of a bipolar IC sense amplifier. The MOS switch and the SA are monolithic integrated. Dynamic test of the subsystem, in which MOS IC switches and bipolar IC SA's are connected in cascaded stages, has indicated that they are capable of 100 Mbit/s return to zero digital signal transmission and 46-dB signal-to-noise ratio.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

基于多值开关级代数的电容模型及其应用

本文应用多值开关级代数为ＭＯＳ电路中的电容建立模型，并提出了应用多值开关级代数分析ＭＯＳ动态电路、时延及电荷共享的方法。     

光控MOS栅固态继电器的电路分析与模拟

光控MOS栅固态继电器是由MOS栅控晶闸管、开关三极管、光电耦合器、增强型MOSFET和齐纳二极管组成的新型开关器件。文章提出了光控MOS栅固态继电器的电路结构，详细分析了它的工作原理及其光电特性。     

Analytical equations for oscillation amplitude of MOS Colpitts oscillator

New analytical equations are presented for amplitude analysis of metal–oxide–semiconductor (MOS) Colpitts oscillator. These equations are obtained from a large signal analysis that includes MOS operation in the saturation, triode and cutoff regions. The analysis is based on a reasonable estimation for the output voltage waveform. The estimated waveform must satisfy the nonlinear differential equations governing the circuit. The validity of the proposed method and the resulting equations has been verified through simulations using TSMC 0.18?µm complementary MOS process. The results are also compared with the other methods. Simulation results show high validity of the proposed equations.     

The detrimental influence of stacking faults on the refresh time of MOS memories

The reverse current of diodes and the storage capability of MOS capacitors were investigated and the detrimental influence of stacking faults in the respective active area is demonstrated. In the case of the relaxation time of MOS capacitors it is shown that their deterioration can be related to the number of the stacking faults in the MOS capacitors resulting in a deterioration of the refresh behaviour of dynamic memories. The influence of one single stacking fault on the dynamic behaviour of a MOS capacitor is demonstrated. From transmission electron microscopy (TEM) and neutron activation analysis it is concluded that stacking faults decorated by Cu or Fe are most harmful to the refresh behaviour.     

Source to drain resistance beyond pinch-off in metal-oxide-semiconductor transistors (MOST)

A detailed analysis is performed yielding source to drain resistance of MOS transistors in the saturation region. The analysis is based on a depletion model of the pinched-off region of the channel. Good agreement is found between theory and experimental results obtained onN-channel silicon MOS transistors (channel length ∼5 µ).     

Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors

The high-frequency thermal noise in the drain and the gate of an enhancement mode MOS field-effect transistor was analyzed by using the transmission line model of the channel. The analysis gave the mean squared noise current generators of the drain and the gate and their correlation. The correlation coefficient of the drain and the gate noise was zero for zero drain voltage and was 0.395j at saturation. The noise figure of the MOS field-effect transistor was calculated from the result of the analysis. The high-frequency noise characteristics of an MOS field-effect transistor were similar to those of a junction gate field-effect transistor.     

Compensating effects in time-dependent dielectric breakdown [MOScapacitors]

Current and cathode electric field data have been measured in a constant-voltage accelerated test of metal-oxide-silicon (MOS) capacitors. The data show that the coefficients in the Fowler-Nordheim equation are: (1) random variables (varying across the MOS capacitors), and (2) have a correlation coefficient of 0.88. The analysis suggests that for typical electric fields used in accelerated testing of MOS capacitors, the standard deviation of log (failure time) increases with decreasing electrical stress     

PLMAP — A piecewise linear MOS circuit analysis program

In this paper we describe a MOS circuit simulation program PLMAP (Piecewise Linear MOS Circuit Analysis Program) which performs efficient time domain simulation of LSI MOS circuits. PLMAP uses a piecewise linear model for MOS transistors. It uses a relaxation method to analyze the piecewise linear circuit at one time point after another. The relaxation method consists of a 2-level decomposition which partitions the whole circuit into 2-level subcircuits and a scheduling method which determines the sequence of analysis of subcircuits. At each time point, the subcircuits are analyzed sequentially and iteratively by using Gauss-Seidel iteration together with a prediction formula to determine the initial guess of solution. Experiences have shown that PLMAP is more efficient in MOS circuit analysis than spice.     

Performance study of n-MOS natural transistor fabricated by low thermal budget process

Natural n-MOS transistor and MOS capacitor test structures have been fabricated by the low temperature process design for better control on device dimensions. Si-SiO₂ interface properties and performance of LPCVD gorwn polysilicon gate natural transistor has been studied through MOS C-V analysis and physical-electrical modeling. Transistor behavior at cryogenic temperatures has also been analysed through MOS C-V characteristics and one dimensional transport equations.     

Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.     

MOS管器件击穿机理分析

讨论了MOS管击穿的分类,以及击穿时场强分布情况,在此基础上,列举和分析了MOS 管击穿的发生区域,主要是结击穿和漏区击穿。文章对雪崩击穿和穿通击穿机理进行了描述,并对 MOS管开启击穿进行了分析。     

MOS capacitor on 4H-SiC as a nonvolatile memory element

Nonvolatile memory characteristics of MOS capacitors are presented in this letter. The MOS capacitors have been fabricated on N-type 4H SiC substrate with nitrided oxide-semiconductor interface. The charge-retention time is in the order of 4.6×10⁹ years, as determined by thermally activated (275-355°C) capacitance-transient measurements and extrapolation to room temperature. The estimated activation energy of the charge-generation processes is 1.6 eV. The results and the analysis presented in this letter demonstrate that 4H SiC MOS capacitors can be used as a memory element in nonvolatile RAMs     

Experimental characterization of power VDMOS transistors incommutation and a derived model for computer-aided design

The authors present an experimental method for the characterization of MOS power switching transistors that does not involve technological parameters that are not available to designers. The method is based on the time-domain analysis of the commutation performance of the transistor when constant current are injected into its terminals. The analysis of the time-domain waveforms and the knowledge of the internal structure of the MOS devices are sufficient for the evaluation of the transistor capacitances. It is then possible to introduce a simple large-signal model for power MOSFETs that is particularly well suited to the analysis of circuits using the MOS transistor in commutation (e.g., switching power converters or high-efficiency power amplifiers). The authors also present the model implementation in the SPICE 2 program. Comparison between results obtained experimentally and by computer simulation for several circuits confirms the accuracy of the proposed method     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

MOS VLSI数字电路分区间时延建模方法

<正> 一、引言 时延模型是逻辑模拟、开关级模拟、定时模拟以及定时分析与验证中的基本问题。目前时延模型大多为经验式的。其分析结果与实际电路时延相差很大。实际电路时延特性的复杂性是造成这种情况的主要原因,晶体管尺寸、阈值电压、基元互联、负载电容、输入波形,以及晶体管在电路中的使用方式等因素都将影响电路的时延。 本文在作者近来工作的基础上,提出了基于时延势概念的一种理论上自洽的时延建模方法,所得模型简单,精度较以往时延模型提高,从而为节点时延势方程理论的实用化奠定了基础。