Variable-length segmental transmission line and its design guidelines

Waveform distortion is a serious problem in higher-frequency signals on printed circuit boards (PCBs). To overcome this problem, we have already proposed the segmental transmission line (STL) method, which divides transmission lines into several segments with different line widths. Each line width is adjusted to make the reflection noises cancel each other out in order to minimize the signal distortion. In this research, we first analyze the waveform reshaping mechanism of STL. Next, we apply STL to a dual in-line memory module (DIMM) clock-line for high-speed computers. The results give helpful guidelines for STL designs, which shows the efficiency of STL. This work was presented in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007     

Digital-signal-waveform improvement on VLSI packaging including inductances

As the digital signal frequency in printed circuit boards (PCBs) increases, waveform distortion, or the signal integrity (SI) problem, is getting more and more serious. The reason the SI problem is becoming serious is that wires or traces need to be regarded as transmission lines which are sensitive to electric noise. In order to overcome this problem, we have proposed a novel methodology called a segmental transmission line (STL), and have shown its effectiveness using computer simulations and fundamental prototypes. However, in the STL design, the combinatorial explosion problem occurs. To solve this problem, a genetic algorithm (GA) was used to design the STL. In this article, we apply the STL to a bus system that includes inductances, which come from the very-large-scale integration (VLSI) packaging. We evaluated the STL in simulation experiments as well as actual experiments using prototypes, and obtained a maximum improvement ratio of 1.53 in the actual experiment.     

高速四相时钟电路设计

基于IHP 130 nm SiGe BiCMOS工艺,设计了一个由基于RC网络相移特性的polyphase移相器和差分时钟缓冲器组成的2 GHz四相时钟电路.因单阶polyphase带宽不足而设计了三阶polyphase级联提高带宽.采用HBT(heterojuntion bipolar transistor)差分时钟缓冲取代MOS(metal oxide semiconductor)单端时钟缓冲,实现更高时钟频率的同时,差分结构也能有效抑制流入采样电容的时钟信号馈通.各模块版图设计均采用高度对称结构来消除相位误差.仿真结果表明,差分输入2 GHz正弦波时,可输出4路相位相差90°方波时钟信号,时钟上升时间约15 ps,4路时钟相位误差小于2.2°,应用到4通道采样保持电路后可成功采样和保持8 GHz正弦输入信号.     

基于AD9361的DQPSK收发工程实现与测试

针对 AD9361实现DQPSK收发过程中存在的工程实现问题,完成了基于SPI接口的AD9361配置,通过测试定位了：输出端无波形、接收与发射本振时域波形扭曲、输出端谐波分量严重、发射本振与接收本振存在随机相位误差四个疑难问题,采用10MHz SPI时钟、系统时钟设置为40MHz、输出端采用1.4GHz、采用点积叉积进行解调四种方法予以解决。结果表明相关问题解决效果良好,所实现的DQPSK收发性能可靠。     

0.001 3 mm2自动频率校正算法电路的设计及应用

在高速串行接口PCIE2.0的设计中,为了保证数据传输的正确性,数据串行传输的工作时钟需要在很短的时间内完成锁定。为了减小锁相环的锁定时间,提高时钟稳定性,在传统的顺序搜索自动频率校正算法电路的基础上,提出了一种新的二进制搜索算法校正电路,并且应用于5 GHz的锁相环中,最大校正时间为22.5 μs。锁相环在SMIC 55 nm CMOS工艺下流片,SS工艺角下,AFC电路的面积为0.001 3 mm2。经测试,锁相环能够快速锁定,性能良好。     

3D‐printed high‐gain circularly polarized antenna for broadband millimeter‐wave communications over the power line

It is well known that high transmission loss occurs when millimeter waves traveling through the atmosphere. As an alternative, power line is proposed as a transmission media to combat the high loss. In this article, a three‐dimensional (3D) printed high‐gain circularly polarized antenna was proposed for millimeter‐wave broadband power line communications. It has a simple structure, where tapered slots are designed between the upper and lower layers of the waveguide to generate the circularly polarized operation. A wide impedance bandwidth of 31.58% (24‐33 GHz) and an axial ratio bandwidth of 28.07% (24.5‐32.5 GHz) are achieved by the proposed design. A maximum gain of 11.2 dBi is measured from the 3D printed structure. The proposed antenna has a simple structure which is easy to adjust to any working frequency. The antenna can be excited by properly integrated to the waveguide that connected to the power line end. The use of 3D printing technology enables a low‐cost solution millimeter‐wave broadband communications over the power line.     

A dual‐band branch line coupler for LTE 0.7 GHz and LTE 2.6 GHz frequencies

In this paper, a dual‐band branch line coupler (BLC) for Long Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed. A dual‐band quarter wave transmission line (DBQWTL) capable to perform dual band operation for frequency ratio >3 is also proposed. The dual band BLC is designed by replacing the quarter wave transmission line of the conventional single band BLC with the proposed DBQWTL. By means of even and odd mode analysis, the closed form design equations of the proposed DBQWTL are obtained. Considering the implementation viewpoint of the proposed BLC, the circuit parameter analysis is carried out. The proposed BLC performs dual band operation with maximum amplitude imbalance of 0.26 dB and phase deviation of 3.07°. It is found in the comparative analysis that the proposed BLC has novelty in terms of its operating frequency ratio range.     

基于FPGA的多通道信号源设计与实现

由于对信号源的质量、灵活性和频率等的要求越来越苛刻,为了满足此需求,设计实现了以FPGA为控制核心,高速D/A芯片AD9739作为数模转换器（DAC）的高质量信号发生器。时钟电路采取外部时钟输入和内部频综输入这两种输入方式,保证了信号源质量、灵活性和可靠性。实现了频率范围为DC-1.25 GHz的宽带信号源设计。利用Chipscope进行调试,连接频谱仪观察现象,测试结果表明该信号源具有精度高、灵活性强、频率响应速度快和杂散少等优点,并在实际工程中取得优异的效果。本设计在实际工程中有很高的应用价值。     

Application of ultra wideband RF energy harvesting by using multisection Wilkinson power combiner

In this study, an ultra‐wide band (UWB) energy harvesting circuit was proposed using the Greinacher rectifier circuit. The circuit was designed with Wilkinson power combiner (WPC) for use at two different radio frequency signal inputs. To enable broadband operation, the multisection Chebyshev impedance matching technique was applied in the branches of the WPC circuit. The center frequency was selected 2.2 GHz in the design. In terms of the parameters of reflection, transmission and isolation, the WPC circuit operates in the 0.4 GHz‐3.4 GHz range and the percentage bandwidth has been calculated as 136%. In the designed Greinacher rectifier circuit, power conversion efficiency (PCE) was analyzed for different input powers. When load resistor selected as R = 1500 Ω, the PCE for the input power of 9 dBm was about 70%. The proposed circuit, where WPC and Greinacher rectifier circuits was used together for energy harvesting; was operated in the frequency ranges BW₁ = 0.4‐0.81 GHz, BW₂ = 1.54‐1.84 GHz, and BW₃ = 2.2 GHz‐2.89 GHz. As a power combining application, dual power inputs were applied to the WPC circuit with frequencies of 540 MHz‐1800 MHz, 540 MHz‐2450 MHz, 540 MHz‐2700 MHz, 800 MHz‐1800 MHz, 800 MHz‐2450 MHz and 800 MHz‐2700 MHz. Eventually, approximately 70.5% PCE and 1.65 V output voltage were obtained.     

A miniature shielded-loop active H-field probe design with high spatial resolution for near-field measurement

A miniature practical active magnetic field (H-field) probe with 0.5 mm × 0.15 mm loop size is designed for electromagnetic interference analysis in electronic systems from 150 kHz to 12 GHz. This probe is fabricated in a four-layer printed circuit board using high-performance and low-loss Rogers material (RO4350B). A low noise amplifier with 14 dB-gain is applied to amplify the radio frequency detect signal. The spatial resolution of the proposed probe is verified under the microstrip with different widths (1.55 and 0.24 mm). In addition, the verification results indicate that the proposed small loop active shielded H-field probe can obtain the better spatial resolution of 422 μm with liftoff = 100 μm. Regarding to the sensitivity of the probe, the proposed probe realizes 16.7 dB μA at 3 GHz with the liftoff = 100 μm. compared with other commercial probes and a reference probe, the proposed probe has better spatial resolution at 150 kHz–12 GHz and sensitivity at 1.5–12 GHz.     

An evolutionary design methodology of printed circuit boards for high-speed VLSIs

As operation frequencies of the printed circuit boards (PCBs) increase in keeping with VLSI frequencies in the GHz domain, two independent serious problems occur in the PCB design. One is waveform distortion problem, or signal integrity (SI) degradation problem, in PCB traces. And the other is power-supply drop problem, or power integrity (PI) degradation problem, in PCB power planes. Those problems are barely able to be overcome on case-by-case empirical designs conventionally. In this paper we newly propose a design approach for each problem, both of which are based on the genetic algorithm. And we obtained improvement ratios of more than double compared with the both conventional designs for SI and PI degradations, respectively.     

X频段八波束接收组件的设计与实现

针对X频段多波束有源相控阵系统的高集成、小型化、多波束等需求,设计了一款高集成、小型化的瓦片式八波束接收组件,该组件基于多层印制板技术,纵向实现了众多有源器件以及八套波束合路网络高密度布局,实现了组件的高集成化;针对组件的八波束合成需求,基于Wilkinson功分器的形式设计了一款小型化的高效合路网络,在7.5-9 GHz范围内,其插入损耗小于13 dB,端口间隔离度小于-20 dB,输出驻波比小于1.2,通道间幅相一致性良好;为降低组件内部信号的传输损耗,对组件内部的垂直互联结构进行了建模分析,得到不同结构参数对其传输性能的影响,通过优化结构参数的方法实现信号的低损耗传输。在此基础上对组件进行了加工实现,经测试,在7.5-9 GHz范围内,组件输出通道增益大于18 dB,输出驻波比小于1.5,通道间相位一致性小于±5°,尺寸仅有80 mm × 80 mm × 7.66 mm。     

用于高精度图像传感器的锁相环

为了提高图像传感器的探测精度,给像素中的传输管提供高精度时钟信号,设计了一款可编程式电荷泵锁相环(Phase-Locked Loop,PLL)模块。该模块使用分频器以输出可调控频率的时钟,增加了复用性;在电荷泵中加入单位增益放大器以消除毛刺,增大了锁相环精度;同时给出了针对整个模块的相位噪声分析。仿真结果表明,当输出200 MHz时钟时,信号的时钟抖动为28 ps,电路工作在1.5 V电压下的功耗<2 mW。该模块已用于一款高精度图像传感器中,在0.11μm CMOS工艺下进行了流片,测试结果表明其可以实现50 MHz到200 MHz的高精度时钟输出,满足了芯片对于时钟的需求。     

基于SRIO传输的高速时钟电路的优化设计

随着系统电路工作频率的不断越高,在应用中对系统互连和电路间的时钟提出了更高的要求。针对在某信号处理系统的设计中,在测试中偶尔出现SRIO链路异常问题,对高速时钟的参数进行了深入分析,发现了时钟信号受到热噪声的影响引起时钟抖动,会导致SRIO链路断开。提出了增加时钟信号的过渡斜率的优化方案,改善了时钟信号的品质,试验证明系统工作稳定可靠,达到了预期效果。     

传输线信号完整性的反射分析

针对高速电路系统的传输线信号完整性问题,通过对高速电路PCB上传输线等效电路的分析,给出了信号传输时产生反射现象的原因;介绍了常用的消除反射的方法,即选择均匀传输线、采用合适的拓扑结构布线和阻抗匹配法,指出阻抗匹配法可解决信号传输的反射现象;阐述了源端阻抗匹配法和负载端阻抗匹配法消除反射的原理和适用条件。针对时钟电路中的反射问题,采用PADS/Hyperlynx软件对阻抗匹配法进行仿真,结果表明,阻抗匹配法能够改善信号传输的反射现象。     

GHz零时滞时钟树物理布图的虚拟通道布线算法

随着集成电路技术的发展和GHz频率的应用需求，已有的基于线长或RC延迟模型的时钟树布图算法已不能适用．针对GHz频率宏模块中时钟树的平面布图，依据流水线技术，提出一种虚拟通道布线算法；根据时钟树的拓扑结构，分别进行粗略布线和虚拟通道内的布线调整，完成时钟树的平面布线．该算法在开发软件原型ClockStar中得以应用．     

Passive intermodulation of printed dipole antennas: Modeling,evaluation, and experiment

A theoretical treatment of electro‐thermally induced passive intermodulation (PIM) is developed for printed dipole antennas, yielding an expression of third‐order intermodulation distortion based on the surface current distribution. The simulation procedure of third‐order PIM products with the full‐wave frequency‐domain method was given to evaluate the PIM level. In particular, the PIM dependencies on input power, two‐tone frequency separation, and substrate parameters are analyzed leading to design guidelines for low distortion antennas. It is shown in this paper that the thermal factors have a noticeable impact on the PIM power generated by printed dipole antennas. Finally, two antenna samples are fabricated on different substrates, Rogers 5880 and FR4, and a two‐tone test at 2‐GHz band using a reflective PIM test system is reported. The PIM evaluation method and the design guidelines to reduce the PIM on printed antennas proposed in this paper are of great significance for telecommunication systems.     

Arbitrary terminated negative group delay circuit using signal interference concept

In this article, we demonstrate signal interference concept based wideband negative group delay (NGD) circuit with an arbitrary termination port impedance. The proposed circuit consists of unequal power division ratio 180° hybrid and in‐phase combiner. The NGD can be generated by controlling power division ratios of 180° hybrid and combiner. For experimental verification, the circuit is designed and fabricated at a center frequency of 2 GHz. The experiment results show that the proposed NGD circuit can provide 460 MHz NGD bandwidth (bandwidth of group delay <0 ns) with group delay of ?0.8 ns at 2 GHz.     

读写通道基于τ因子内插时钟恢复模型设计与实现

读写通道是介于磁盘读写头与设备控制器之间的电子电路,实现数据写入和可靠的恢复。伺服信号采样时钟是伺服信号检测的重要组成部分,其设计的目标是在提高伺服信号传输速率的同时维持低的误码率,这就对通道的数据采样处理以及时钟恢复电路的设计提出了严格的要求。本文通过对读写通道伺服的分析,对常用的由锁相环构成的伺服时钟恢复电路进行改进,在线性插值时钟恢复的基础上提出了基于τ因子内插时钟恢复模型,并推导出τ因子插值滤波器系数算法,还给出了伺服时钟恢复的硬件及FPGA的设计与实现方案,最后给出了基于线性插值和基于τ因子内插时钟恢复试验。测试结果证明,采用基于τ因子内插滤波器模型可以获得更好的谐波频谱。