Capacity of wireless dynamic TDMA and media access control for packetized voice/data integration

We obtain the capacity of wireless dynamic TDMA for packetized speech and investigate its stability characteristics depending upon the ratio between request slots and message slots. We analyze this system based on an imbedded Markov chain approximation and validate its performance by simulation. We also propose a new media access control for voice/data integration and investigate its performance by simulation     

Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems

A methodology for the hierarchical partitioning and mapping of digital signal processing (DSP) tasks to heterogeneous local cluster based network of very large scale integration (VLSI) processors is presented. The goal is to achieve rapid prototyping of VLSI DSP systems. The high level partitioning issues of DSP task graphs and the proposed metrics to guide the partitioning process are described in this paper. Partitioning tominimize power inefficiency in the DSP system is one important metric addressed by this work, since low power signal processing is paramount to new portable and high density multi-chip module (MCM) DSP systems. The application of theRatio Cut Partitioning approach to DSP graphs is explained. We illustrate our results with examples and show how the final partitions vary depending upon the target architecture to meet rapid prototyping requirements. We compare our approach with known techniques and show that it works much better for our target applications.     

Performance evaluation of a reservation random access scheme for packetized wireless systems with call control and hand-off loading

We consider a packet switched wireless network where each cell's communication channel is shared among packet voice sources. In this paper, we present a method for the design and analysis of wireless cells using a reservation random access (RRA) scheme for packet access control. This scheme is integrated with a call admission control procedure. We model the state process of a single cell as a vector Markov chain. We compute the steady state distribution of the Markov chain. This result is used to calculate the packet dropping probability and the call blocking probability. By setting limits on maximum permissible levels for the call blocking probability and the packet dropping probability, we obtain the Erlang capacity of a single cell, with and without hand-off traffic. For an illustrative RRA scheme, the Erlang capacity of a single cell is shown to be about twice that attained by a comparable fixed assigned TDMA scheme. We show that a cellular network using this RRA scheme and which applies can be no blocking of hand-off calls, exhibits similar call capacity levels.This work is supported by a University of California MICRO and Pacific-Bell Grant No. 94-107.     

Power control and capacity analysis for a packetized indoormultimedia DS-CDMA network

This paper proposes a packetized indoor wireless system using direct-sequence code-division multiple-access (DS-CDMA) protocol. The indoor radio environment is characterized by slow Rayleigh fading with or without lognormal shadowing. The system supports multimedia services with various transmission rates and quality of service (QoS) requirements and allows for seamless interfacing to asynchronous transfer mode (ATM) broadband networks. All packets are transmitted with forward error correction (FEC) using convolutional code for voice packets and Bose-Chaudhuri-Hocquenghem (BCH) code for data packets with an automatic retransmission request (ARQ) protocol and for video packets without ARQ. A queueing model is used for servicing data transmission requests. A power control algorithm is proposed for the system, which combines closed-loop power control with channel estimation to give the best performance. The cell capacity of each traffic type and various multimedia traffic configurations in both single-cell and multiple-cell networks are evaluated theoretically under the assumption of perfect power control. The effect of power control imperfection on the capacity using the proposed power control algorithm is investigated by computer simulation     

Compact NMOS building blocks and a methodology for dedicated digital filter applications

Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 /spl mu/m NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 /spl mu/m technology, in terms of silicon area and speed. These compact results are achieved due to proper minimization in the design. The experience with the above designs is then generalized into a methodology for custom digital filters. An important concern is a hardware-minimization scheme over all design levels (algorithm, bit-serial architecture, and layout style) with efficient IC implementation and performance in mind. It leads to the possibility of an automated design. The design is supported by computer aided design tools for design verification on all levels, and for file management as well as layout. A formal design of a third-order elliptical wave digital filter demonstrates the concept. The resulting chip area is 1.8 mm/SUP 2/ in 6 /spl mu/m NMOS. The simulated maximum bit rate is 5 MHz (corresponding to 312 kHz sampling rate), with a power consumption of 18 mW.     

Deriving use cases for distributed systems from knowledge requirements

Knowledge requirements for distributed systems express desired states of affairs concerning initial and final knowledge of the components of a system. It is shown how use cases (i.e. sets of scenarios) can be obtained from knowledge requirements. The technique involves the use of event structures that specify use cases capable of achieving the requirements, and logical postconditions for events. The technique allows design refinement, both in the form of architectural refinement and in the form of event refinement. The correctness of refinements can be checked by checking logical implications. As an example, use cases and scenarios for a simple mobile telephony protocol, based on GPRS (the data extension of GSM) are derived, on the basis of the corresponding knowledge requirements. Scenarios are given in the form of message sequence charts.     

Performance of PRMA: a packet voice protocol for cellular systems

Equilibrium point analysis is used to evaluate system behavior in a packet reservation multiple access (PRMA) protocol based network. The authors derive the probability of packet dropping given the number of simultaneous conversations. The authors establish conditions for system stability and efficiency. Numerical calculations based on the theory show close agreement with computer simulations. They also provide valuable guides to system design. Because PRMA is a statistical multiplexer, the channel becomes congested when too many terminals are active. For a particular example it is shown that speech activity detection permits 37 speech terminals to share a PRMA channel with 20 slots per frame, with a packet dropping probability of less than 1%     

数码相机USB端口测试系统

随着表面贴装技术的发展,表面贴装零件的尺寸不断缩小,印刷电路板上零件密度增大,给印刷电路板及零件的测试带来困难.USB端口测试系统作为测试数码相机主板USB端口功能的工具,通过构建一个USB host来替代实际计算机.单片机AT89C52与USB芯片CH375能构建出USB host,满足生产线上大批量生产测试的需求.     

Modeling and design methodology for mechatronic systems

The integration of mechanical systems and microelectronics opens many new possibilities for process design and automatic functions. After discussing the mutual interrelations between the design of the mechanical system and digital electronic system the different ways of integration within mechatronic systems and the resulting properties are described. The information processing can be organized in multi levels, ranging from low level control through supervision to general process management. In connection with knowledge bases and inference mechanisms, intelligent control systems result. The design of control systems for mechanical systems is described, from modeling, identification to adaptive control for nonlinear systems. This is followed by solving supervision tasks with fault diagnosis. Then design tools for mechatronic systems are considered and examples of applications are given, like adaptive control of electromagnetic and pneumatic actuators, adaptive semiactive shock absorbers for vehicle suspension, and electronic drive-chain damping.     

校园数字化语音系统的构建与分析

数字语音系统是为解决教学语音问题而设计开发的软件系统,它突破了硬件版语音教室在实际应用中的技术障碍和成本限制,以电脑网络为基础,只需一张系统安装光盘,即可建立集语音教室、多媒体教室、考试中心等多功能合一的专业教学环境,最大限度简化学校采购、排课、使用、维护及升级工作,大幅度降低投资成本。使用数字语音系统可以依照授课老师所设计的教学计划,对学生进行讲解、讨论、分组或个别的口语练习,强调锻炼学生的听说读写译等各方面的专业技能。数字语音系统将影音视频、图形图像、动画以及文字等各种多媒体信息以及控制实时动态地引入到教学过程中,教学手段比传统语音教室更全面更先进。     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

Packet dropping analysis for reservation voice TDMA systems

We analyze the packet dropping performance in an ideal reservation time-division multiple-access (TDMA) multiplexing voice system with the focus on the probability distribution of the number of packets dropped in a particular talkspurt. Our analysis method is based on the discrete three-state Markov speech model which corresponds to the voice source equipped with a fast speech activity detector (SAD). The numerical results for a system of 14 slots/frame reveal that the probability of losing several packets in a talkspurt is much higher than expected (by geometric distribution) and thus not negligible     

Design considerations for a receiver for digital fibre-optic communication systems

An approach to design easily a receiver for digital fibre-optic communication systems is given. In particular, a 34.368 Mbit/s communication system is analysed, where little or no avalanche-detector gain is used.     

Obtaining schedules for digital systems

A systematic technique is presented to derive correct schedules for a synchronous digital system, given a signal flow graph for an algorithm. It is also shown how to use this technique to derive designs that are optimal in having the lowest latency, the highest throughput, or the smallest number of registers. The same technique can also be used to verify digital systems that have already been designed     

一种新型的数字图像/话音传输系统的实现方案

提出了一种采集与传输数字图像／话音的方法,介绍了其总体方案以及设计重点,包括乒乓存储结构的改进、数据复接和控制逻辑的实现等。     

A structured methodology for assessing and improving e-services in digital cities

Many cities all over the world are making large investments for the construction of big network infrastructures, in order to offer to local public organizations, businesses and citizens high speed connectivity, and on top of them useful e-services, aiming to achieve various social and economic objectives. The value generated from these costly ‘digital city’ investments is actually the value provided to the citizens and businesses by the e-services that will be developed and run on these network infrastructures. This paper proposes and validates a structured methodology for assessing and improving e-services developed in digital cities. The proposed methodology assesses the various types of value generated by an e-service, and also the relations among them, allowing a more structured evaluation, a deeper understanding of the value generation process and also identification and prioritization of the improvements that should be made in the e-service with the usually scarce resources in municipalities. This methodology is applied for the evaluation of an e-learning service developed in the Greek city of Karlovassi for young citizens, and also for the prioritization of the necessary improvements in it. The above application provided positive and encouraging evidence concerning the validity, usefulness and applicability of the proposed method.     

UVM-based verification methodology for RFID-enabled smart-sensor systems

Universal verification methodology (UVM) is a standardized methodology for verifying integrated circuit designs. In this contribution, we present a UVM-based verification methodology for verifying mixed-signal smart-sensor systems. Our approach permits the validation of system functionality before implementation and also to verify the implementation on various levels of abstraction. The model-based verification approach enables to build a scalable and reusable framework, in which assertions and constrained-random stimuli are used to monitor and also to verify mixed-signal-system behavior automatically. A comprehensive example of an radio-frequency identification-based smart-sensor mixed-signal system used for bioanalytical applications is presented. Along with the designed UVM test bench architecture, we describe a novel solution for estimating the power consumption of the digital sub-system using application-specific random-activity patterns generated during UVM test bench runs (Neumann et al., Synthesis Modelling Analysis and Simulation Methods and Application to Circuit Design, SMACD, 2012).