数字化中频数据传输接收机系统设计

软件无线电是从射频到基带的全面的数字化的理论。但由于目前器件发展水平的限制,从中频开始实现软件无线电是一种切实可行的方式。介绍了一种中频数字化的QPSK数据传输系统的设计,并且基于软件无线电中的可重配置理论,采用模块化的设计方法,将各部分功能用独立的模块来实现,以方便重复使用。     

一种雷达数字中频接收机处理方法与实现

提出了和、差三通道雷达数字中频接收机的一种处理方法.该方法采用数字下变频将中频信号转换为正交视频信号,使用数字自动增益控制提高接收机的动态范围,通过相参积累和数字鉴频提取多普勒频率,根据和、差比幅提取方位和俯仰角误差,并以调节差通道本振初相的方式实现和、差通道幅相一致性校正.给出了用单片现场可编程门阵列实现数字中频接收机处理的具体方法.通过对接收机的实际测试表明,处理测量精度满足系统要求.     

多通道雷达中频数字接收机的工程实现方法研究

根据中频直接采样与数字下变频的基本原理,实现多通道数字中频接收,给出了工程实现的方法和测试结果。在较高中频上采样并进行后续处理,结果满足系统设计指标,且可以简化接收机的设计。     

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption     

DC-coupled IF stage design for a 900-MHz ISM receiver

This paper presents a DC-coupled 900-MHz ISM band RF front-end for a short-range wireless receiver. The front-end, fabricated in a 0.5-/spl mu/m CMOS process, is intended as a test vehicle to verify the proposed DC-coupled topology. In this topology, a low-frequency feedback circuit suppresses the DC offset and low-frequency noise at the mixer output. The DC-coupled topology is compared with traditional AC coupling. We show that there is a tradeoff between bandwidth and midband loss in a fully integrated AC-coupled system. The proposed DC-coupling technique does not impose this tradeoff. The DC-coupled topology was verified via simulation and measurements from the test vehicle.     

A time-interleaved recursive loop band-pass delta-sigma modulator for a digital IF CDMA receiver

A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-/spl mu/m CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm/sup 2/.     

基于FPGA的中频数字化接收机系统实现

介绍了一种基于附的中频数字化接收机的硬件设计，给出总体设计方案，主要部件及参数的设计方法，讨论了高阶腿滤波器在附中采用分布式算法实现。最后测试结果表明此系统合理可靠且满足设计要求。     

数字中频接收机信号处理的研究

大规模集成电路的发展使得数字中频采样收发机的实现成为现实。本文使用宽带中频数字化方案,利用FPGA中的IP核把经过AD转换后的中频信号通过数字下变频处理为基带信号,并利用Matlab中的Dspbuilder提供的IP核得到了总体的仿真结果。该接收系统用于WCDMA移动通信网络的基站体系中,能很好地实现手机信号覆盖和传输。     

数字下变频器HSP50214B在中频数字接收机中的应用

数字下变频器（DDC）对侦察接收机的软件化设计至关重要,给出中频数字接收机数字下变频电路实例．实现了数字侦察接收机对多种调制样式信号的高性能处理,展示了数字下变频器HSP50214B在中频数字接收机中的灵活应用。     

数字下变频器HSP50214B在中频数字接收机中的应用

数字下变频器(DDC)对侦察接收机的软件化设计至关重要,给出中频数字接收机数字下变频电路实例,实现了数字侦察接收机对多种调制样式信号的高性能处理.展示了数字下变频器HSP50214B在中频数字接收机中的灵活应用.     

数字语音解码器的低功耗设计策略

主要从系统级、算法级、结构级等多个层面综合考虑减少数字语音解码器的功耗.系统级使用双向不交叠时钟技术,在提高耗时长的模块运算频率的同时消除了电路的竞争与冒险;算法级主要使用汇编语言重写和优化原代码,既可以压缩源代码,更能充分挖掘硬件的运算潜力;在结构级,主要利用并行技术,增加协处理器进行并行计算,有效提高运算速度.另外在布局布线时使用全定制集成电路设计技术手工布线,大为减少解码器的芯片面积.     

MSK扩频接收机中放系统设计

本文提出了采用MSK信号格式的 3种扩频接收机中放系统模型 ,并用计算机模拟的方法分析比较了几种典型的干扰环境下 3种系统的性能 ,文中给出的曲线可供设计MSK扩频通信系统参考。     

Least-squares design technique for digital Hilbert-transform filters

Discrete-time calculation of Hilbert transforms is of increasing importance in digital processing of communication signals. The technique for designing digital Hilbert filters described here makes use of the properties specific to this filter category in arriving at a simple closed-form matrix formulation. The optimality criterion utilised is that of least-squares error (l.s.e.), which results in filter error characteristics that compare reasonably well with minimax designs using the Remez exchange algorithm?achieved with considerably reduced computational burden.     

A new design for digital adaptive filters

The design and operation of a digital adaptive filter based on a modified Widrow-Hoff algorithm is described. It uses LSI components as main elements. This filter realization converges faster than other realizations reported hitherto because its weight vector is updated at every sampling instant.     

Linear phase decimation and interpolation filters for high-speedapplications

A novel hardware realisation for linear phase decimation and interpolation FIR filters, exploiting the symmetry of the coefficients to reduce the number of multipliers, is described. Combining the multiplications, leads to contra-dataflow or folded filter structures in which simple pipelining is limited, because of the opposite directions of the data flows. It is shown that these structures can be transformed into new filter structures, which allow conventional pipelining to relax the timing demands for high-speed applications     

Improved design procedure for multiplierless FIR digital filters

An algorithm is presented for the design of finite impulse response filters, yielding filter coefficients that are either single powers of two, or sums or differences of two powers of two. In all cases tried this algorithm gives simpler realisations compared both to conventional design methods and to other multiplierless design algorithms.<>     

Minimax design of recursive digital filters with a latticedenominator

The authors deal with the problem of minimax recursive digital filter design with a lattice structure for the denominator. The design problem is formulated so that the coefficients for the numerator and denominator of a recursive filter can be found by solving the best linear complex Chebyshev approximation (LCCA). A design technique based on the weighted least-squares algorithm previously proposed by one of the authors is then developed for solving the resulting LCCA problem. During the design process, this technique finds the tap coefficients for the numerator and the reflection coefficients for the denominator simultaneously. The stability of the designed recursive filter is ensured by incorporating an efficient stabilisation procedure to make all of the reflection coefficient values fall between -1 and +1. Computer simulations show that the proposed technique provides better design results than existing techniques     

中频数字化光端机的研究与设计

本文主要介绍一种中频信号数字化传输设备.该设备将用户的中频模拟数据信号经数字化处理后通过光纤进行远距离传输,并在接收端还原成模拟数据信号和用户的终端设备进行通信.本套设备克服了传统的模拟设备在传输过程中接收灵敏度低、成本高、动态增益小、不易控制等缺点.     

基于数字变带宽的雷达数字中频信道化设计

在雷达中频数字信道化中为了简化实现多种带宽的设计要求,提出了数字变带宽设计方法改变接收信道的带宽。首先,与传统的模拟变带宽的设计方法比较分析表明,该方法具有降低多带宽接收信道设计复杂程度的优点;然后,通过建立理论模型,对其进行仿真和分析,理论原理可行。最后通过实测某雷达回波信号进行验证,仿真结果和实测结果基本一致。结果表明,该方法不影响接收信道输出信噪比,同时又能简单实现接收信道的多种带宽改变,具有可行性和工程实用性。     

Strategies for design automation of high speed digital filters

Optimization techniques for DSP circuits are described based on the design experience with a number of high-speed digital filter chips. These designs show that efficient high speed digital filter designs can be achieved using several optimizations at the architecture, circuit, and layout level. The problems of automating these optimizations in a general DSP synthesis environment are discussed, and possible CAD solutions are proposed.