A 55-V, 0.2-mΩ-cm2 vertical trench power MOSFET

Experimental results that demonstrate trench power MOSFETs with a specific on-state resistance of 0.2 mΩ-cm² and capable of sustaining 55 V across drain-source terminals in the off state are discussed. This performance was achieved by using an improved silicon trench processing technology. The forward conductivity reported is the highest ever obtained for a silicon power device     

Large-area, 8-cm2 GaAs solar cells fabricated from MBEmaterial

A GaAs solar cell with an area of 2 cm×4 cm fabricated from a film grown by molecular beam epitaxy (MBE) on a 5.08-cm-diameter GaAs substrate is discussed. This is the largest device ever fabricated from MBE material. The cell demonstrated an efficiency of 21.7% under one-sun AM1.5 conditions at 25°C and 18.8% under one-sun AM0 conditions at 28°C     

A 300-MPOS video signal processor with a parallel architecture

A 300-MOPS image digital signal processor (IDSP) including four pipelined date processing units and three parallel input-output (I/O) ports has been developed using a 0.8-μm BiCMOS technology. The IDSP integrates 910000 transistors in a 15.2-mm×15.2-mm area using a macrocell-oriented building-block design environment. The power dissipation was reduced to 1.0 W per 25-MHz instruction cycle, and a TTL-compatible I/O interface was retained by implementing two power supplies-one providing 3 V and the other 5 V. With this performance, a single-board 64/128-kb/s video codec was implemented with four IDSPs     

Packet video and its integration into the network architecture

Packet video is investigated from a systems point of view. The most important issues relating to its transmission are identified and studied in the context of a layered network architecture model, leading to a better understanding of the interactions between network and signal handling. The functions at a particular layer can thereby be made less dependent on network implementation and signal format. In the layered network model, the higher layers provide format conversion, hierarchical source coding, error recovery, resynchronization, cost/quality arbitration, session setup and tear-down, packetization, and multiplexing. Provisions from the network layers pertain mainly to real-time transmission. Special consideration is given to hierarchical source coding, error recovery, statistical behavior, and timing aspects. Simulation results indicating practical solutions to some of the issues raised are presented for a hierarchical packet-video subband coding system     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications

A MIMD based multiprocessor architecture for real-time video processing applications consisting of identical bus connected processing elements has been developed. Each processing element contains a RISC processor for controlling and data-dependent tasks and a Low Level Coprocessor for fast processing of convolution-type video processing tasks. To achieve efficient parallel processing of video input signals, the architecture supports independent processing of overlapping image segments. Running at a clock rate of 40 MHz, a single processing element provides a peak performance of 640 Mega arithmetic operations per second (MOPS). For the real-time processing of basic video processing tasks like 3×3 FIR-filter, 8×8 2D-DCT and motion estimation, a single processing element provides a sufficient computational rate for video signals with Common Intermediate Format (CIF) at a frame rate up to 30 Hz. For hybrid source coding of CIF video signals at a frame rate of 30 Hz a multiprocessor system consisting of six processing elements is required. A linear speedup of the multiprocessor system compared to a single processing element is achieved. A VLSI implementation of a processing element in 0.8 µm CMOS technology is under development.     

A 220-mm2, four- and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture

A 220-mm², 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC₄ current to ~90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ~1400 faults/chip with only 8% chip overhead     

H2+和D2+谐波强度与波长的关系

为了了解H₂+及其同位素分子谐波光谱效率与激光波长之间的关系,采用求解2维薛定谔方程的方法,理论研究了600nm~1600nm激光波长下H₂+和D₂+谐波光谱强度随波长的变化关系。结果表明,光谱强度随波长增大而减小;在短波长区间,H₂+光谱强度减小的倍率要大于D₂+,在长波长区间,H₂+光谱强度减小的倍率要小于D₂+;此外,在弱光强下,H₂+光谱强度总是大于D₂+, 在强光强下,H₂+光谱强度在短波长区间小于D₂+, 而其在长波长区间大于D₂+; 核间距延伸和电荷共振增强电离在H₂+和D₂+谐波光谱强度变化上起到主要作用。这一结果对分子谐波调控是有帮助的。     

A video DSP with a macroblock-level-pipeline and a SIMD typevector-pipeline architecture for MPEG2 CODEC

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V     

An 0.35-μm, 6-mΩ, 43 μΩ-cm2 lateralpower MOSFET for low-voltage, megahertz switching powerapplications

Power MOSFET technology has to be improved significantly in order to address the needs of very low voltage power conversion applications such as that powers the future microprocessor. Detailed studies by the author indicate that device technology that is suitable for this type of application is not the conventional vertical power MOSFET technology; instead, a lateral power MOSFET technology based on the VLSI technology is more suitable. In this letter, we report for the first time the experimental result of a 6-mΩ, 43 μΩ-cm² lateral power MOSFET based on 0.35-μm VLSI design rule. With a gate-charge of only about 3 nC, in terms of on-resistance gate-charge product, these results are the best ever reported for sub-20-V power MOSFET     

A 7F2 cell and bitline architecture featuring tiltedarray devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F² DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 μm technology. This concept features an advanced 30° tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip     

A low-noise folded bit-line sensing architecture for multigigabitDRAM with ultrahigh-density 6F2 cell [CMOS design]

The 6F² cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F² DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F² cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F² cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed     

2n prime-sequence codes and coding architecture foroptical code-division multiple-access

Recent study shows that optical code-division multiple-access (CDMA) networks cannot be evaluated or designed by only considering the performance (i.e., correlation properties) of the optical pseudo-orthogonal codes selected. The structures of optical encoders and decoders are another important factors to consider and are needed to coordinate with the selected optical codes as much as possible. A special family of 2ⁿ codes, so-called 2ⁿ prime-sequence codes, is constructed. A general theorem on the cardinality of the new codes is provided. The properties and performance of the codes are also studied. Since these codes pose the algebraic properties of both prime-sequence and 2ⁿ codes, new optical encoding and decoding structures are designed to optimize the system parameters (e.g., power budget and cost) of these optical CDMA networks. This new configuration is particularly attractive for ultrafast optical processing and waveguide implementation for tile future high-capacity, low-loss, all-optical CDMA networks     

A high-speed parallel sensing architecture for multi-megabit flashE2PROMs

A high-speed parallel sensing architecture for high-density 5-V-only flash E²PROMs is described. A source-biasing technique enhanced the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same work line are sensed simultaneously. Self-time dynamic sensing was developed for high speed and stable sensing and also decreased read disturbance and operating current. Simulated results show that a sub-10-μA cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size     

A low noise 230 GHz heterodyne receiver employing 0.25-μm2 area Nb-AlOx-Nb tunnel junctions

The authors report recent results for a full-height rectangular waveguide mixer with an integrated IF matching network. Two 0.25 μm ² Nb-AlO_x-Nb superconducting-insulating-superconducting (SIS) tunnel junctions with a current density of ≈8500 A/cm² and ωRC of ≈2.5 at 230 GHz have been tested. One of these quasiparticle tunnel junctions is currently being used at the Caltech Submillimeter Observatory in Hawaii. Detailed measurement of the receiver noise have been made from 200-290 GHz for both junctions at 4.2 K. The lowest receiver noise temperatures were recorded at 239 GHz, measuring 48 K DSB at 4.2 K and 40 K DSB at 2.1 K. The 230-GHz receiver incorporates a one-octave-wide integrated low-pass filter and matching network which transforms the pumped IF junction impedance to 50 Ω over a wide range of impedances     

用于白光LED的红色荧光粉SrAl2Si2O8:Eu3+,Li+的制备和发光性能研究

采用高温固相法制备了Sr1－x Al₂Si₂O₈:Eu³⁺ x,Li⁺0.03系列红色荧光粉,研究了试样的晶体 结构和发光性质。合成的试样均为纯相的SrAl₂Si₂O₈晶体,单斜晶系,空间群为 C2/m(12); Eu³⁺和Li⁺进入基质晶体中,使得SrAl₂Si₂O₈晶胞参数a、b和c 略微减小,只引起了晶体结构轻 微的畸变。试样的激发光谱由位于220~580nm波长的一个宽激发带 和一组锐线峰构成,其中 395nm波长处Eu³⁺的⁷F₀→⁵L₆激发峰的强度最强。发射光谱位于550~750nm波长范围内呈现多 条锐 线发射,其中595nm和615nm波长处发射峰最 强,分别归属于Eu³⁺的⁵D₀→⁷F₁磁偶极跃迁和⁵D ₀→⁷F₂电偶极跃迁。研究了Eu³⁺浓度对荧光粉发光性能的影响, 结果表明,随着Eu³⁺浓度的增 加,发光强度先增加后减小,最佳掺杂量为0.03,而对试样的色坐标 几乎没有影响;该系列荧光粉浓度淬灭机理为电偶极–电偶极(d-d)相互作用。     

A 76-mm2 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-μm 2-metal CMOS technology. A small die of 76 mm² and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 μm²; 2) a new hierarchical wordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacitor size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain architecture with these new techniques reduces die size to 65% of that of the conventional FeRAM. Moreover a ferroelectric capacitor overdrive scheme enables sufficient polarization switching, without overbias memory cell array. This scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5-V V_dd operation. Thanks to fast cell plateline drive of chain architecture, the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 ns, at 3.0 V so far reported     

Al3+/Eu2+共掺杂高硅氧玻璃的荧光特性

由纳米多孔玻璃制备了Al3+/Eu2+共掺杂的高硅氧玻璃,并研究了在纳米多孔玻璃基质中共掺杂Al3+离子对Eu2+离子450 nm处蓝色荧光强度和荧光峰位的影响。结果表明,共掺杂Al3+离子可分散多孔玻璃中丛聚的Eu2+离子,加之Al2O3较低的声子能量,使Eu2+离子的蓝色荧光发射显著增强;并且由于共掺杂的Al3+降低了Eu2+离子5d轨道劈裂幅度,随着Al3+离子含量的增加,Eu2+离子荧光峰蓝移。     

偏振光谱法观察Na_2A~1∑_u~+～b~3Ⅱ_u微扰能级的超精细结构

在分子光谱和量子化学领域中，Na_2分子的结构和光谱的重要性是众所周知的。对于Na_2单重态的激光光谱研究已经得到了大量的结果。相比之下，Na_2三重态的研究则困难得多，因为从其基态（？）到三重态的跃迁是偶极禁戒的。尽管如此，人们还是找到了直接研究三重态的途径，这就是通过（？）微扰能级观察三重态。