Hardware-software codesign of embedded systems

Designers generally implement embedded controllers for reactive real-time applications as mixed software-hardware systems. In our formal methodology for specifying, modeling, automatically synthesizing, and verifying such systems, design takes place within a unified framework that prejudices neither hardware nor software implementation. After interactive partitioning, this approach automatically synthesizes the entire design, including hardware-software interfaces. Maintaining a finite-state machine model throughout, it preserves the formal properties of the design. It also allows verification of both specification and implementation, as well as the use of specification refinement through formal verification     

Hardware/software interface codesign for embedded systems

Separate hardware- and software-only engineering approaches cannot meet the increasingly complex requirements of embedded systems. HW/SW interface codesign would enable the integration of components in heterogeneous multiprocessors. The authors analyze the evolution of this approach and define a long-term roadmap for future success.     

Model-based codesign

Hardware-software codesign has been a research topic since the beginning of this decade (1990s), but only now are structured methods emerging that focus on automating design. Unfortunately, to date most codesign approaches leverage performance from individual hardware and software tools, rather than enforcing a structured integration of hardware and software systems simultaneously. A few frameworks have successfully done this integration and have the potential for significant benefits, including reduced time to market, smaller scale design, better likelihood of component reuse, and maximum use of processing power. The article describes a codesign approach that lets developers create models of a formal system representation independently of the hardware and software implementation. The authors' framework, which targets embedded systems, lets developers use simulation based modeling to explore the feasibility of virtual prototypes and then interactively map the specification onto a software-hardware architecture     

A codesign approach for distributed systems

Distributed systems have become prevalent in response to the rapidly expanding Internet's demands. Their design presents new challenges because it involves the interaction of hardware and software. Continual marketplace innovation drives computing toward heterogeneity in both hardware and software and generates a complexity that goes beyond the earlier codesign approaches, which were developed for more homogeneous systems executing in non-distributed environments. Codesign of heterogeneous systems requires the support of a powerful modeling and simulation environment because analysis alone cannot deal with all the challenges such complex systems pose. We believe that modeling and simulation, using the discrete-event system specification modeling and simulation framework, are the most suitable vehicles to study the complexities associated with developing distributed-object computing systems     

Computer-aided hardware-software codesign

Most digital systems consist of a hardware component and software programs that execute on the hardware platform. Obviously, a system can deliver higher performance when we tune the hardware to its software applications and vice versa. Today's novel architectures and the possible use of computer-aided design tools have created new opportunities to find solutions to codesign problems. This survey addresses this challenge, considers different architectures and their uses, and reports on the status of CAD codesign tools, with particular reference to simulation and synthesis     

基于EFL中间件平台的嵌入式灵活安全系统

随着嵌入式系统的广泛应用,系统安全问题已经成为一个急需解决的问题。针对嵌入式系统功耗和性能均衡等方面的特点,基于EFL中间件平台实现了自适应的灵活安全中间件。该系统基于EFL中间件技术和和欣操作系统,提供了一个可灵活配置的构件化安全系统来解决嵌入式系统的安全问题。     

A security approach for off-chip memory in embedded microprocessor systems

This paper describes a complete off-chip memory security solution for embedded systems. Our security core is based on a one-time pad (OTP) encryption circuit and a CRC-based integrity checking module. These modules safeguard external memory used by embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. Our implementation limits on-chip memory space overhead to less than 33% versus memory used by a standard microprocessor and reduces memory latency achieved by previous approaches by at least half. The performance loss for software execution with our solution is only 10% compared with a non-protected implementation. An FPGA prototype of our security core has been completed to validate our findings.     

A framework for hardware/software codesign

It is argued that a hardware/software codesign methodology should support the following capabilities: integration of the hardware and software design processes; exploration of hardware/software tradeoffs and evaluation of hardware/software alternatives; and model continuity. A codesign methodology that supports many of these capabilities is outlined. The methodology is iterative in nature and serves to guide codesign exploration with the uninterpreted/interpreted modeling approach. It integrates performance (uninterpreted) models and functional (interpreted) models in a common simulation environment     

Synthesis steps and design models for codesign

Codesign is a joint development of hardware and software components to obtain a complete system design. The fields of specification, design, and synthesis of mixed hardware/software systems are becoming increasingly more popular. The paper provides a taxonomy of codesign and discusses some design environments and models     

A hardware-software codesign methodology for DSP applications

The authors describe a systematic, heterogeneous design methodology using the Ptolemy framework for simulation, prototyping, and software synthesis of systems containing a mixture of hardware and software components. They focus on signal-processing systems in which the hardware typically consists of custom data paths, finite-state machines (FSMs), glue logic and programmable processors. The software is one or more embedded programs running on the programmable components     

A codesign approach for safety-critical automotive applications

This complex, bus-based air bag ignition system for automobiles demonstrates an effective way to design embedded fault-tolerant applications     

Chip-package codesign for high-frequency circuits and systems

When the need for high frequency combines with the demand for low-cost consumer electronics, the challenge of ensuring correctly functioning components becomes paramount. Focusing on chip-package codesign offers a solution     

Chip-package codesign flow for mixed-signal SiP designs

Design engineers are challenged with two separate entities: the chip and package designs. Because system-in-package integrates multiple dies into a package, design engineers should have a tool to easily combine the two entities. This article demonstrates a seven-die SiP design that implements a chip-and-package codesign platform using available EDA tools.     

A model and methodology for hardware-software codesign

A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioral synthesis, software compilation, and demonstration on a testbed consisting of a commercial central processing unit (CPU), field-programmable gate arrays, and programmable interconnections. Design examples that illustrate how certain characteristics of system behavior and constraints suggest hardware or software implementation are presented     

Sizzle: A standards-based end-to-end security architecture for the embedded Internet

According to popular perception, public-key cryptography is beyond the capabilities of highly constrained, “mote”-like, embedded devices. We show that elliptic curve cryptography not only makes public-key cryptography feasible on these devices, it allows one to create a complete secure web server stack that runs efficiently within very tight resource constraints. Our small-footprint HTTPS stack, nicknamed Sizzle, has been implemented on multiple generations of the Berkeley/Crossbow motes where it runs in less than 4 KB of RAM, completes a full SSL handshake in 1 s (session reuse takes 0.5 s) and transfers 1 KB of application data over SSL in 0.4 s. Sizzle is the world’s smallest secure web server and can be embedded inside home appliances, personal medical devices, etc., allowing them to be monitored and controlled remotely via a web browser without sacrificing end-to-end security.     

浅析基于嵌入式系统网络安全的研究

现代计算机技术与互联网技术的快速发展使各个领域越来越关注基于嵌入式系统的安全性能问题,对嵌入式系统网络安全性能的研究也成为网络安全领域的一个重要课题。针对嵌入式网络系统的安全问题,在分析了目前网络安全体系不足的基础之上,将IPSec和SSL协议相结合,提出了一种嵌入式网络系统安全策略的解决方案。     

基于嵌入式虚拟化技术的手机安全方案

分析了当前手机领域面临的安全问题和现有手机安全解决方案的不足。提出了一种基于轻量级执行环境的嵌入式系统虚拟化模型;并在该模型的基础上实现了新的手机安全解决方案。通过仿真实验,可以证明该方案以极小的性能代价提高了手机系统的安全性。     

Domain-specific regular acceleration

The regular model-checking approach is a set of techniques aimed at exploring symbolically infinite state spaces. These techniques proceed by representing sets of configurations of the system under analysis by regular languages, and the transition relation between these configurations by a transformation over such languages. The set of reachable configurations can then be computed by repeatedly applying the transition relation, starting from a representation of the initial set of configurations, until a fixed point is reached. In order for this computation to terminate, it is generally needed to introduce so-called acceleration operators, the purpose of which is to explore in one computation step infinitely many paths in the transition graph of the system. A simple form of acceleration operator is one that is associated to a cycle in the transition graph, computing the set of states that can be obtained by following this cycle arbitrarily many times. The computation of acceleration operators is strongly dependent on the type of the data values that are manipulated by the system, and on the symbolic representation chosen for handling sets of such values. In this survey, we describe acceleration operators suited for the regular state-space exploration of systems relying on FIFO communication channels, as well as those based on integer and real variables.     

Hardware-software codesign using processor synthesis

A new tool aids concurrent hardware-software development of processors for embedded systems. Pilot programs using ProcSyn achieved significant cost and time savings and, in some cases, improved the quality of the final product