Utilizing a novel root companding transform technique to reduce PAPR in OFDM systems

One major defect in orthogonal frequency division multiplexing systems is the high peak‐to‐average power ratio (PAPR) at the transmitter. The linear nonsymmetrical transform (LNST) technique, one of the companding transform (CT) techniques for PAPR reduction, offers excellent performance, but requires additional side information. In this paper, a new ‘root CT’ technique without additional side information is proposed, and it can reach a good trade‐off between the PAPR reduction and the bit error rate (BER). The theoretical analysis of the proposed root technique is also derived. The simulation results show that the proposed root CT technique can achieve more efficient PAPR reduction and better power spectrum density than those of the LNST technique. The BER of the proposed CT technique without additional side information is close to that of the LNST technique with additional side information when the AWGN or multipath fading channels are considered. Furthermore, the simulation results also demonstrate that the proposed technique offers better performance than that of the µ‐law technique over the AWGN and multipath fading channels. Copyright © 2010 John Wiley & Sons, Ltd.     

Fuzzy approach to speech synthesis

An approach to speech synthesis using fuzzy logic and distinctive features parametrisation of the input signal is outlined. The basic idea is that phonetic transitions can be linguistically described in terms of spectral features. Possible applications of this approach are given     

PSM: an object-oriented synthesis approach to multiprocessor systemdesign

Although multiprocessor systems are becoming a trend today, few synthesis tools currently available can actually automate the design of multiprocessor systems. Performance synthesis methodology (PSM) is an object-oriented system-level synthesis approach to multiprocessor system design. Since PSM was designed specifically for the synthesis of multiprocessor systems, it is not only much more efficient when synthesizing parallel systems, but also produces better parallel systems than currently available uniprocessor system-level synthesis tools. Colored Petri nets used in modeling system components and object modeling technique used in the design process have both contributed to the shortening of system development time and to the reduction of design cost. First, user specification consisting of functional models and performance constraints is translated into architecture models. Then, the system is configured by selecting the method of control, the memory organization, the type of processor, and the type of system interconnection. Finally, a heuristic design space exploration algorithm is used to generate several near-optimal design alternatives. The best architecture is chosen by evaluating the design alternatives using a flexible performance estimation formula that mainly considers system level design features, such as system throughput, utilization, reliability, scalability, fault-tolerance, and cost. Several systems were successfully synthesized using this top-down object-oriented PSM, thus showing its feasibility as a design automation tool for parallel systems     

RLC-ladder-network synthesis: signal-flow-graph approach

Using signal-flow graphs, a theorem is proved which gives the immittance functions of the ladder network of which the voltage transfer function is to be realised, and then the realisation of a given voltage transfer function by the use of this theorem is illustrated.     

Energy-efficient skewed static logic with dual Vt: design and synthesis

In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S/sup 2/L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-/spl mu/m CMOS technology and verified that S/sup 2/L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S/sup 2/L is developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.     

A unified framework for opportunistic fair scheduling in wireless networks: a dual approach

In this paper, we propose a unified framework for opportunistic fair scheduling in wireless systems. We consider a TDMA type of multiple access scheme, in which only one user can be scheduled in each time-slot. For opportunistic fair scheduling in such a system, some nice frameworks have been developed in the previous works, such as Agrawal and Subramanian (Allerton conference on communication, control and computing, 2002), Liu et al. (IEEE Journal of Selected Areas in Communications 19(10): 2053–2065, 2001) and Liu et al. (Computer Networks 41(4): 451–474, 2003). However, in this paper, we consider a more general problem that can accommodate more general types of fairness, and more general types of utility functions than those in the previous works. In addition to those generalizations, we develop a new framework for opportunistic fair scheduling based on the duality theory, which is different from those in the previous works. The duality theory is a well-defined theory in the mathematical optimization area. Hence, it can provide a unified framework for many different types of problems. In fact, we show that two different frameworks in Agrawal and Subramanian (Allerton conference on communication, control and computing, 2002), Liu et al. (IEEE Journal of Selected Areas in Communications 19(10): 2053–2065, 2001) and Liu et al. (Computer Networks 41(4): 451–474, 2003) are special cases of ours. In addition, by using the unified framework developed in this paper, we can not only develop various opportunistic fair scheduling schemes but also analyze the developed algorithm more rigorously and systematically.     

基于过零点-极点估计的瞬时频率幅度算法

Hilbert-Huang变换(HHT)理论通过经验模态分解(EMD)提取信号的内蕴模态函数(IMF),并对IMF利用Hilbert变换得到信号的时频幅度谱和边际谱。在总结Hilbert变换理论和算法实现局限性的基础上,提出基于过零点-极点估计求取IMF瞬时频率、幅度算法,通过对离散信号插值运算精确求取过零点和极点位置,并据此求出相应点的瞬时频率和幅度,最后采用三次样条求取信号的瞬时频率幅度曲线。通过几个典型的例子对该算法进行检验,结果表明,与Hilbert变换结果比较,借助该算法得到信号的时频幅度谱和边际谱结果更精确、频率分辨率更好。     

A general approach to synthesis and analysis of quasi-resonantconverters

A method for systematic synthesis of quasi-resonant (QR) topologies by addition of resonant elements to a parent pulse-width modulation (PWM) converter network is proposed. It is found that there are six QR classes with two resonant elements, including two novel classes. More complex QR converters can be generated by a recursive application of the synthesis method. Topological definitions of all known and novel QR classes follow directly from the synthesis method and topological properties of PWM parents. The synthesis of QR converters is augmented by a study of possible switch realizations and operating modes. In particular, it is demonstrated that a controllable rectifier can be used to accomplish the constant-frequency control in all QR classes. Links between the QR converters and the underlying PWM networks are extended to general DC and small-signal AC models in which the model of the PWM parent is explicitly exposed. Results of steady-state analyses of selected QR classes and operating modes include boundaries of operating regions, DC characteristics, a comparison of switching transitions and switch stresses, and a discussion of relevant design trade-offs     

A unified approach to short-time Fourier analysis and synthesis

Two distinct methods for synthesizing a signal from its short-time Fourier transform have previously been proposed. We call these methods the filter-bank summation (FBS) method and the overlap add (OLA) method. Each of these synthesis techniques has unique advantages and disadvantages in various applications due to the way in which the signal is reconstructed. In this paper we unify the ideas behind the two synthesis techniques and discuss the similarities and differences between these methods. In particular, we explicitly show the effects of modifications made to the short-time transform (both fixed and time-varying modifications are considered) on the resulting signal and discuss applications where each of the techniques would be most useful The interesting case of nonlinear modifications (possibly signal dependent) to the short-time Fourier transform is also discussed. Finally it is shown that a formal duality exists between the two synthesis methods based on the properties of the window used for obtaining the short-time Fourier transform.     

An optimization approach to the synthesis of multichiparchitectures

An optimization approach to the high level synthesis of VLSI multichip architectures is presented in this paper. This research is important for industry since it is well known that these early high level decisions have the greatest impact on the final VLSI implementation. Optimal application-specific architectures are synthesized here to minimize latency given constraints on chip area, I/O pin count and interchip communication delays. A mathematical integer programming (IP) model for simultaneously partitioning, scheduling, and allocating hardware (functional units, I/O pins, and interchip busses) is formulated. By exploiting the problem structure, using polyhedral theory, the size of the search space is decreased and a new variable selection strategy is introduced based on the branch and bound algorithm. Multichip optimal architectures for several examples are synthesized in practical cpu times. Execution times are comparable to previous heuristic approaches, however there are significant improvements in optimal schedules and allocations of multichips. This research breaks new ground by 1) simultaneously partitioning, scheduling, and allocating in practical cpu times, 2) guaranteeing globally optimal architectures for multichip systems for a specific objective function, and 3) supporting interchip communication delay, interchip bus allocation, and other complex interface constraints     

Deterministic signals and interference in FM reception: The "Instantaneous" approach, with undistorted inputs

The purposes of this study are several: 1) to extend earlier models of the FM reception process, to include as much "realism"-i.e., nonideality of both the linear and nonlinear elements of the typical FM receiver-as possible, and still retain analytical and computational feasibility; 2) to examine explicit cases of interference produced by one or more deterministic signals; and 3) with such specific examples, both to provide insights into the distortion effects generated by the nonlinar interactions of the various (desired and undesired) signals in the receiver and to present the analytical framework of the instantaneous outputs required in any (subsequent) fully statistical treatment, where now the interference (e.g., "noise") is noticeably non-Gaussian. In addition, these deterministic models may also provide useful structures for simulation studies. The instantaneous receiver outputs are obtained for the following receiver models (A) and interference "scenarios" (B). For (A), (I) "superclipping" and an ideal discriminator; (II) no limiting and ideal discriminator; (III) "superclipping" and a nonideal discriminator; (IV) no limiting and a nonideal discriminator. For (B), with each (A), we consider explicitly the cases of: (i)one cochannel interfering signal; (ii) one adjacent channel interferer, and (iii) M symmetrical interferers (M = 1, 5). All the above are obtained here for idealized (i.e., sufficiently wide-band) RF-IF receiver stages, which are essentially linear under this condition. The results are illustrated with cases for selected, typical parameters of the combination of the interference-receiver structure.     

An artificial intelligence approach to active filter synthesis

This paper deals with a novel active filter synthesis method using artificial intelligence (AI). The AI-based synthesis methodology uses original analog circuit representation performed by a Prolog backward-chaining inference mechanism. Circuit representation is specified as an analog circuit language to describe filter topologies, performance characteristics, and subcircuits. Synthesis is organized as a Prolog searching program based on backward-chaining strategy to transform input specifications into an appropriate filter structure. The Prolog program performs symbolic equation transformations to proper filter transfer characteristics. The proposed synthesis methodology has been developed for integrated continuous-time filter structures using operational transconductance amplifiers and capacitors to realize tunable and active C filters. A synthesis program has been implemented in Turbo Prolog on an IBM PC AT computer, and a filter example is presented demonstrating the use of the program.This paper was supported by the Ministry of Education of Poland Grant CPBP 02.14.     

Time domain approach to recursive digital filter synthesis

The problem of the design of IIR digital filters, when the analog filter has been synthesized, resides in the approximation of a continuous system by means of a discrete one. We present a synthesis method which discretizes an Input-State-Output (I-S-O) model of the analog filter and is completely performed in the time domain. The basis of the method is the way in which the problem is stated, which points out the fundamental role played by the interpolator and allows an easy implementation.The main advantages of our method, with reference to traditional approaches, are:

• •- it allows direct working on continuous representations of the analog filter and the discretization does not require symbolic calculations as in approaches based on substitution techniques (for example bilinear transformation);
• •- it is completely numerical and is very simple from a computational point of view;
• •- it can be used for single and multiple input-output filters;
• •- it allows longer sampling periods using suitable interpolators.

An example is discussed which allows a comparison with the synthesis method based on bilinear transform and shows, also, that computing time may be saved as the sampling period may be traded off with the interpolator order.     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

Comments on: “Reduction of peak-to-average power ratio ofOFDM system using a companding technique”

The authors comment on the work of Xianbin Wang, Tjhung, and and Ng (see ibid., vol.45, no.3, 1999). They add that Wang et al. present a very elegant analysis of the symbol error rate in a companded COFDM system. A comment that they make is that it seems that the noise power was constant, while the transmitted signal's power was increased as it was companded. It would in our opinion be more meaningful to compare the performance of the companded signal to that of an uncompanded signal of equal power     

Path switching: a technique to tolerate dual rail routing imbalances

Dual Rail Precharge (DRP) circuits, which are theoretically secure against differential power analysis attacks, suffer from an implementation problem: balancing the routing capacitance of differential signals. To solve this, four proposals have been put forward: Divided Wave Dynamic Differential Logic (DWDDL) (Tiri and Verbauwhede in DATE ’04, pp. 246–251, [2004]), FatWire (Tiri and Verbauwhede in Cardis 2004, pp. 143–158, [2004]), Backend Duplication (Guilley et al. in Lecture Notes in Computer Science, vol. 3659, pp. 383–397, [2005]) and Three Phase Dual Rail (Bucci et al. in Lecture Notes in Computer Science, vol. 4249, pp. 232–241, [2006]). Of these, three (DWDDL, FatWire, Backend Duplication) proposals alter the routing mechanism of Standard Place and Route tools, which in turn introduces an additional step. The other proposal introduces a third phase which reduces the system’s performance. In this paper we propose a new countermeasure, Path Switching, to address the routing problem in DRP circuits. From SPICE simulations we show that our proposal does not reveal the secret key for up to 300,000 traces, an increase of 75 times over normal Dual Rail circuits and 3000 times over normal single rail circuits.     

The dual parameterization approach to optimal least square FIRfilter design subject to maximum error constraints

This paper is concerned with the design of linear-phase finite impulse response (FIR) digital filters for which the weighted least square error is minimized, subject to maximum error constraints. The design problem is formulated as a semi-infinite quadratic optimization problem. Using a newly developed dual parameterization method in conjunction with the Caratheodory's dimensional theorem, an equivalent dual finite dimensional optimization problem is obtained. The connection between the primal and the dual problems is established. A computational procedure is devised for solving the dual finite dimensional optimization problem. The optimal solution to the primal problem can then be readily obtained from the dual optimal solution. For illustration, examples are solved using the proposed computational procedure     

Instantaneous frequency and energy distribution of a signal

A theory is derived on a signal representation in an instantaneous frequency vs. time plane. It is observed that the usual frequency vs. time representation does not give a specific pattern for the signal. It is shown that by switching the frequency axis to an instantaneous frequency axis, and by distributing the energy of the signal on an instantaneous frequency vs. time plane it is possible to build up a coherent theory. As an example, patterns of speech signals (sustained vowels) are represented.