Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8–2 GHz bandwidth.     

一种高频周期信号的低频采样方法

在模拟信号转换为数字信号的过程中,对转换结果影响最大的是采样频率的设定,针对采样频率的设定受到Nyqu ist定理的限制,传统的模拟信号数字化系统可以处理的模拟信号频率较低的现状,文中主要从理论上推导和证明了一种突破Nyqu ist定理的限制方法,使用这种方法可以在模拟信号转换为数字信号的系统中,使用较低采样频率对高频率周期信号进行采样。从而能够使数字处理技术得到更加广泛的应用。     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

Broadband multicarrier communication receiver based on analog to digital conversion in the frequency domain

This paper introduces a multicarrier communication receiver for broadband applications based on analog to digital conversion (ADC) of the received signal in the frequency domain. The samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since It efficiently parallelizes the A/D conversion reducing the sampling speed requirements. We show that the sampling rate requirements are relaxed as the number of frequency samples is increased, which introduces a trade-off between complexity and sampling rate. The new receiver possesses additional advantages, including scalability with increasing frequency samples, the possibility of optimally allocating the available number of bits for the ATD conversion across the frequency domain samples which potentially reduces the distortion introduced by the high-speed ADC, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers. We also investigate how the proposed receiver responds to common multicarrier communication receiver problems such as phase noise and channel frequency selectivity.     

基于数/模混合预失真技术的功放线性化北大核心CSCD

随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。     

星载AIS信号的带通采样与恢复

针对卫星接收机对模拟器件性能要求较高的问题,提出直接对接收到的射频信号进行采样,将模拟信号转换成数字信号,后续处理用软件模块实现的方法。同时结合自动识别系统( AIS )本身两个载波频率接近以及带宽较窄的特点,根据Nyquist带通抽样定理实现以较低速率采样来获取船舶状态信息,研究了一种星载AIS信号全数字解调方法和信息检测恢复技术。首先介绍了带通采样原理,其次详细研究了多用户AIS信号采样频率的确定、两个频道信号分离方法以及单通道信号如何下变频为基带信号,其中基带信号检测采用简化的基于Viterbi的非相干检测方法,最后结合AIS协议进行信号的恢复,并通过示波器采集实际船台发送的AIS信号进行了实验,验证了该过程的正确性。     

星载AIS信号的带通采样与恢复

针对卫星接收机对模拟器件性能要求较高的问题,提出直接对接收到的射频信号进行采样,将模拟信号转换成数字信号,后续处理用软件模块实现的方法。同时结合自动识别系统（AIS）本身两个载波频率接近以及带宽较窄的特点,根据Nyquist带通抽样定理实现以较低速率采样来获取船舶状态信息,研究了一种星载AIS信号全数字解调方法和信息检测恢复技术。首先介绍了带通采样原理,其次详细研究了多用户AIS信号采样频率的确定、两个频道信号分离方法以及单通道信号如何下变频为基带信号,其中基带信号检测采用简化的基于Viterbi的非相干检测方法,最后结合AIS协议进行信号的恢复,并通过示波器采集实际船台发送的AIS信号进行了实验,验证了该过程的正确性。     

The Japanese scene [digital HDTV]

Japan is the only country, so far, to be actually broadcasting high-definition television services. MUSE (multiple sub-Nyquist sampling encoding) is the basis for systems applying bandwidth compression to the transmission of both analog and digital signals. It encodes a signal of 1125 lines and 60 fields per second, a high-definition television (HDTV) signal into an 8-Hz bandwidth. Experimental MUSE broadcasts started in 1990 and have continued ever since. Meanwhile, work has been in progress in areas other than MUSE. Enhanced-definition television, a terrestrial system, is entering its second generation. Integrated digital broadcasting looks to spin many services into a single digital thread for transmission over a single channel. Digital sound broadcasting and hierarchical television transmission will also come in for consideration. The MUSE system depends on digital technology for signal processing, but the HDTV signal that is broadcast is analog, the outcome of frequency modulation     

Ultra-wideband analog-to-digital conversion via signal expansion

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.     

A new interpolation technique for time interleaved \Upsigma\Updelta A/D converters

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65?nm CMOS process.     

一种基于时间展宽的光模数转换技术

基于时间展宽的光模数转换技术通过在采样量化之前对模拟信号进行时域上的展宽,可大大提高模数转换器（ADC）的性能。介绍了这种技术的基本原理,分析了基于此技术的并行ADC采样结构的性能,并对该结构与传统并行采样结构进行了比较,结果证明,该技术具有高采样率、大有效输入带宽以及高分辨率等优势。     

A power-adaptable A/D converter with integrated data compression

A novel adaptable analog/digital converter (ADC) that combines analog/digital conversion and entropy-coding for integrated data compression and low-power operation is reported. The converter has high flexibility of operation in terms of adaptable resolution, conversion rate and input signal statistics. This feature allows to adaptively react to changes of the situation and to put the device in each case into the optimum configuration. The ADC has been realized in a 0.6 μm CMOS technology with a peak resolution of 12 bit and 200 kS/s maximum sampling rate. A comprehensive power model of the converter is presented that reflects precisely the power consumption determined from experiments. The model is very useful for optimizing the converter configuration in the node of a wireless sensor network for specific situations. A feasible real-life application is demonstrated.     

一种先进的TTL超高速比较器

文章介绍了一种新型TTL超高速比较器，并对其工作原理、制作工艺、技术性能及可靠性设计等进行了简要描述。该产品具有工作电压低（ 3V)、功耗小（6mA)、响应时间快（10ns)等显著特点，可以广泛应用于高速时序逻辑、线性接收器、数字通讯、模拟信号高速采样以及PCMCIA卡等领域。     

孔径抖动对中频采样系统信噪比影响的研究

孔径抖动对中频(或射频)带通采样系统信噪比的影响非常严重.理论上,尽管相同带宽的中频信号和基带信号可以用相同的频率进行采样,但中频采样受孔径抖动等因素的影响更大,其采样技术要求也更高.如果在中频采样系统中解决不好孔径抖动问题,很可能根本采集不到正确的信号.本文通过分析孔径抖动产生的原因,孔径抖动与ADC (模数转换器)的信噪比以及与被采样信号上限频率之间的关系,找出了由孔径抖动决定的被采样信号的上限频率与ADC模拟带宽之间存在差距的原因,并发现了过采样率与处理增益及孔径抖动之间的关系.最后,介绍了几项减小孔径抖动的具体措施.     

基于光采样的瞬时测频技术研究

传统高频微波信号瞬时测频(Instantaneous Frequency Measurement,IFM)技术受模拟数字转换器(Analog To Digital Converter,ADC)影响很大.提出了一种新的光采样方法,放弃传统的ADC,利用光强度调制器将高频微波信号调制到低重复频率采样光脉冲上,进而达到光采样的目的.利用快速傅里叶变换(Fast Fourier Transform,FFT)结合线性调频z变换(Chirp-z Transform,CZT)的方法,提高频谱分辨率,对欠采样条件下产生的频率余数进行准确估计,进而通过中国余数定理对信号频率进行重构.实验模拟表明,该方法可以对39 GHz带宽内信号频率进行准确测量.     

利用插值法提高采样率的滤波器设计

随着数字信号的迅速发展,在现代数字系统中对超过单一采样率的处理已经越来越普遍,这直接导致了多采样率处理作为数字信号处理(DSP)中一个新的分支领域的出现。其中在进行D/A(数字/模拟)转换的场合,往往需要提高数字信号采样率来降低对模拟滤波器的要求。论述利用插值的方法来提高采样速率,介绍了内插原理和给出了一种多相滤波器的设计方法,使性能和资源占有率得到较大的突破,最大限度地减少资源消耗。     

宽带直扩信号的随机解调压缩采样方法

为了有效解决扩频测控通信系统宽带化带来的高速采样压力和高数据率问题,提出了基于压缩感知的直扩信号随机解调压缩采样方法。通过对模拟信号压缩采样原理进行研究,深入分析和推导随机解调采样原理及其数学模型,提出了基于压缩感知的直扩信号采集系统构架,并对压缩比取值影响因素进行了分析;给出了随机解调压缩采样系统硬件实现方案,并对其可行性进行了分析;最后对所提出的直扩信号压缩采样方法的性能进行了仿真分析。仿真结果表明,压缩采样系统可以实现直扩信号的压缩采样处理,并能够高精度重构原信号,但重构信号的解调门限会随压缩比增大而相应提高,这是采样率降低所需付出的代价。压缩采样为宽带直扩测控通信系统提供了一种高效的模数转换和同步解调处理思路。     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

基于FPGA实现简易数字频率计的设计

简易数字频率计的设计,采用FPGA实现对模数转换芯片A/Dtlc549的控制,对外来信号采样,实现信号从模拟到数字的转换,在单位时间内通过计数器的累加实现对频率的计数。该设计实现的频率精度为1Hz,测量范围为0～100MHz,经实际电路测试,仿真结果表明,该频率计具有较高的实用性和可靠性。     

多通道高速ADC电路PCB设计技术浅谈

ADC是将模拟信号转换为数字信号的芯片,它在电路系统中的作用决定了它必然和其它大量数字电路一起使用,所以在其PCB设计中除了需要考虑一般PCB设计中要注意的问题之外,还要在多方面引起特别注意,尤其是在高速应用中。本文就针对多通道高速ADC电路设计的特点,以E2V公司的EV10AQ190芯片为例,重点讨论了包含多通道高速ADC的硬件电路设计中印刷电路板布局时所必须引起注意的问题,包括数字地和模拟地。数字电源和模拟电源的处理,ADC输入信号的隔离问题,采样时钟的处理和输出信号的阻抗匹配等问题。