All optical half adder based on photonic crystal resonant cavities

In this paper, we are going to propose and design an all optical half adder based on photonic crystal structures. For realizing the proposed structure, we will use two nonlinear resonant cavities inside a two-dimensional photonic crystal structure. Nonlinear resonant cavities will be created by replacing the ordinary rods via defect rod made of nonlinear material such as doped glass. Plane-wave expansion and finite difference time domain methods will be used for simulating the proposed structure. For the proposed structure, the maximum delay time is about 3 ps.     

Carry-select adder using single ripple-carry adder

Instead of using dual carry-ripple adders, a carry select adder scheme using an add-one circuit to replace one carry-ripple adder requires 29.2% fewer transistors with a speed penalty of 5.9% for bit length n=64. If speed is crucial for this 64 bit adder, then two of the original carry-select adder blocks can be substituted by the proposed scheme with a 6.3% area saving and the same speed     

An electrooptical adder

A prototype for a binary adder, in which the carry propagation is handled by light signals is suggested, thus enabling a fast execution of addition operation even for large operands.     

CMOS analogue adder

A CMOS analogue circuit is proposed that computes the sum of two voltages. The circuit is self-biased, only requires a small number of transistors, and offers good accuracy over a wide range of input values. The design makes no special demands on device aspect ratios and could offer an economic alternative to conventional approaches. Simulation results have shown that total harmonic distortion (THD) is lower than -40 dB for output voltages up to 4 V peak to peak     

A fast VLSI adder architecture

An architecture for performing fixed-point, high-speed, two's-complement, bit-parallel addition by using the carry-free property of redundant arithmetic and a fast parallel redundant-to-binary conversion scheme is presented. The internal numbers are represented in radix-2 redundant digit form, and the inputs and the output of the adder are represented in two's-complement binary form. The adder operands are added first in a radix-2 redundant adder to produce the result in radix-2 digit (-1, 0, 1) form. This result is converted to two's-complement binary form using the parallel conversion scheme. The high-speed conversion for long words is achieved through the use of a novel sign-select operation. The proposed adder, referred to as the sign-select conversion adder, is faster than all previous high-speed two's-complement binary adders for large word lengths. The implementation is highly regular with repeated modules and is very well suited for VLSI implementation     

A p-n-p-n binary full adder

Describes the theory and design principle. By making use of the regenerative characteristics of p-n-p-n devices, a binary full adder circuit is designed. A computer-aided circuit analysis program is used to calculate circuit equations and to choose the external elements. The calculated response of the circuit agree with the experimental results.     

An area-time efficient NMOS adder

A model of computation for VLSI systems has been developed based on the Mead and Conway approach. This model accommodates the fan-out dependency in NMOS technology. Based on this model, a method for producing area-time efficient carry lookahead adders in NMOS has been developed. This method coordinates between the structural level (cells and interconnections) and the physical layout level (size of individual transistor). The proposed procedure exhibits modularity and regularity. Finally, an example of designing a 4-bit adder is given.     

DPTL 4-b carry lookahead adder

Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1-μm non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890×0.652 mm² (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers)     

Low voltage Manchester adder design

A low voltage dynamic Manchester adder design is presented, with a critical delay path operating at a higher voltage level. This voltage level is generated on-chip using a bootstrapping circuit. The goal of this design is to maintain the delay of its worst-case path, comparable to the design having a higher supply voltage, while operating the rest of the circuit at a lower supply voltage, thus consuming less overall power. A SPICE simulation is performed to verify the design     

The noncooperative binary adder channel

Jamming is studied as a game in the binary adder channel. The legal user controls simultaneously the encoder and the decoder by the choice of a key; the jammer controls the channel by the choice of an interference signal. For any given pair of encoder and decoder, this leads to a two-person zero-sum game. It is shown that this game can be solved in many cases of interest. In particular, an exact measure of performance is derived for the class of so-called direct sequence systems.     

Energy efficient hybrid adder architecture

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.     

Pipelined GaAs carry lookahead adder

Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 μm E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to reduce the power budget are essential. As a result. The design of a four bit pipelined GaAs CLA operating at 800 MHz and exhibiting less than 1.8 mW of power dissipation is presented     

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays than the existing designs.     

Memristor based N-bits redundant binary adder

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the theoretical advantages of the redundant binary system, and to eliminate the carry (borrow) propagation using signed digit representation. The advantage of carry elimination in the addition process is that it makes the speed independent of the operands length which speeds up all arithmetic operations. One memristor is sufficient for both the addition process and for storing the final result as a memory cell. The adder operation has been validated via different cases for 1-bit and 3-bits addition using HP memristor model and PSPICE simulation results.     

Low voltage CMOS full adder cells

A formal design procedure for realising a minimal transistor CMOS XOR-XNOR cell using pass networks is presented that successfully scales down with power supply voltage and fully compensates for the threshold voltage drop in MOS transistors. A full adder using this cell is also presented     

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.     

Self-timed Manchester chain carry propagate adder

The authors present a self-timed adder that uses two Manchester chains to propagate carries in a two-rail code. With the inclusion of buffers in the chains, the adder met the timing conditions typical of an asynchronous design based on the `bundled-data, bounded-delay' model and is significantly faster than self-timed adders with restoring logic and similar complexity     

Single flux quantum one-decimal-digit RNS adder

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm². Chips were fabricated at HYPRES, Inc. using 1 kA/cm² low-T_c Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.     

Tunnel diode full binary adder circuit

A simple full binary adder circuit employing a tunnel diode and a transistor is proposed. It has a well defined operation and is capable of operating at rates up to 200 MHz.