All optical half adder based on photonic crystal resonant cavities

In this paper, we are going to propose and design an all optical half adder based on photonic crystal structures. For realizing the proposed structure, we will use two nonlinear resonant cavities inside a two-dimensional photonic crystal structure. Nonlinear resonant cavities will be created by replacing the ordinary rods via defect rod made of nonlinear material such as doped glass. Plane-wave expansion and finite difference time domain methods will be used for simulating the proposed structure. For the proposed structure, the maximum delay time is about 3 ps.     

Carry-select adder using single ripple-carry adder

Instead of using dual carry-ripple adders, a carry select adder scheme using an add-one circuit to replace one carry-ripple adder requires 29.2% fewer transistors with a speed penalty of 5.9% for bit length n=64. If speed is crucial for this 64 bit adder, then two of the original carry-select adder blocks can be substituted by the proposed scheme with a 6.3% area saving and the same speed     

An electrooptical adder

A prototype for a binary adder, in which the carry propagation is handled by light signals is suggested, thus enabling a fast execution of addition operation even for large operands.     

CMOS analogue adder

A CMOS analogue circuit is proposed that computes the sum of two voltages. The circuit is self-biased, only requires a small number of transistors, and offers good accuracy over a wide range of input values. The design makes no special demands on device aspect ratios and could offer an economic alternative to conventional approaches. Simulation results have shown that total harmonic distortion (THD) is lower than -40 dB for output voltages up to 4 V peak to peak     

A p-n-p-n binary full adder

Describes the theory and design principle. By making use of the regenerative characteristics of p-n-p-n devices, a binary full adder circuit is designed. A computer-aided circuit analysis program is used to calculate circuit equations and to choose the external elements. The calculated response of the circuit agree with the experimental results.     

An area-time efficient NMOS adder

A model of computation for VLSI systems has been developed based on the Mead and Conway approach. This model accommodates the fan-out dependency in NMOS technology. Based on this model, a method for producing area-time efficient carry lookahead adders in NMOS has been developed. This method coordinates between the structural level (cells and interconnections) and the physical layout level (size of individual transistor). The proposed procedure exhibits modularity and regularity. Finally, an example of designing a 4-bit adder is given.     

Pipelined GaAs carry lookahead adder

Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 μm E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to reduce the power budget are essential. As a result. The design of a four bit pipelined GaAs CLA operating at 800 MHz and exhibiting less than 1.8 mW of power dissipation is presented     

Energy efficient hybrid adder architecture

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.     

The noncooperative binary adder channel

Jamming is studied as a game in the binary adder channel. The legal user controls simultaneously the encoder and the decoder by the choice of a key; the jammer controls the channel by the choice of an interference signal. For any given pair of encoder and decoder, this leads to a two-person zero-sum game. It is shown that this game can be solved in many cases of interest. In particular, an exact measure of performance is derived for the class of so-called direct sequence systems.     

Phase-Locked Loop based frequency adder

The Phase-Locked Loop (PLL) frequency adder is based on the fractional N technique which is successfully applied in the frequency synthesis field. This method may be used to add two frequencies /tf₁ and /tf₂, i.e., to give a one frequency equal to /tf₁ + /tf₂. The only a priori information needed is to know that /tf₁>/tf₂ and that /tf₁//tf₂ is a rational number. The proposed method may be effectively implemented by inexpensive digital logic or on a microprocessor when the input frequencies are not too high. This method may be easily extended to frequency subtraction.     

Self-repairing adder using fault localization

In this paper we propose an area-efficient self-repairing adder that can repair multiple faults and identify the particular faulty full adder. Fault detection and recovery has been carried out using self-checking full adders that can diagnose the fault based on internal functionality, independent of a fault propagated through carry. The idea was motivated by the common design problem of fault propagation due to carry in various approaches by self-checking adders. Such a fault can create problems in detecting the particular faulty full adder, and we need to replace the entire adder when an error is detected. We apply our self-checking full adder to a carry-select adder (CSeA) and show that the resulting self-checking CSeA consumes 15% less area compared to the previously proposed self-checking CSeA approach without fault localization. After observing fault localization with reduced area overhead, we utilize the self-checking full adder in constructing a self-repairing adder. It has been observed that our proposed self-repairing 16-bit adder can handle up to four faults effectively, with an 80% probability of error recovery compared to triple modular redundancy, which can handle only a single fault at a time.     

Low voltage Manchester adder design

A low voltage dynamic Manchester adder design is presented, with a critical delay path operating at a higher voltage level. This voltage level is generated on-chip using a bootstrapping circuit. The goal of this design is to maintain the delay of its worst-case path, comparable to the design having a higher supply voltage, while operating the rest of the circuit at a lower supply voltage, thus consuming less overall power. A SPICE simulation is performed to verify the design     

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays than the existing designs.     

Memristor based N-bits redundant binary adder

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the theoretical advantages of the redundant binary system, and to eliminate the carry (borrow) propagation using signed digit representation. The advantage of carry elimination in the addition process is that it makes the speed independent of the operands length which speeds up all arithmetic operations. One memristor is sufficient for both the addition process and for storing the final result as a memory cell. The adder operation has been validated via different cases for 1-bit and 3-bits addition using HP memristor model and PSPICE simulation results.     

Low voltage CMOS full adder cells

A formal design procedure for realising a minimal transistor CMOS XOR-XNOR cell using pass networks is presented that successfully scales down with power supply voltage and fully compensates for the threshold voltage drop in MOS transistors. A full adder using this cell is also presented     

Fast two's complement VLSI adder design

The design by Srinivas and Parhi (1992) which used redundant-number adders for fast two's complement addition is re-examined. The underlying mechanism is revealed and improvements are presented which lead to a static-logic binary-tree carry generator to support high speed adder implementations with a delay of [log₂(N)]+2 gates     

A novel multiplexer-based low-power full adder

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.     

A high-speed adder using Gunn diodes

A high-speed adder employing Gunn diodes is proposed. The system is constructed by using the threshold logic technique for high-speed carry propagation. Since all inputs of n stages with each weight are simultaneously applied to the anode of each Gunn diode to generate the nth carry at once, the operating speed of the adder should be considerably improved.     

Tunnel diode full binary adder circuit

A simple full binary adder circuit employing a tunnel diode and a transistor is proposed. It has a well defined operation and is capable of operating at rates up to 200 MHz.