提高多元胞结构半导体放电管浪涌能力的研究

讨论了半导体放电管能量损耗对其浪涌能力的影响.结果表明减小长基区宽度可以明显地降低器件的开通和通态能量损耗,从而有效提高器件的浪涌能力.     

改进SSPD浪涌吸收能力的工艺研究

介绍了用于宽带快速信息传输系统的半导体瞬态浪涌保护器件（ＳＳＰＤ）在小的器件面积和小的器件电容情况下,提高ＳＳＰＤ浪涌吸收能力的工艺方法。理论分析和实验结果都说明,关键是减少基区总宽度,而在制备工艺中设法减少基区少子寿命的衰减也是有效措施之一。     

元器件与组件

低电容晶闸管浪涌保护器NP0080、NP0120和NP0160低电容、低泄漏晶闸管浪涌保护器件(TSPD)采用节省空间的TSOP-5封装,在发生浪涌和静电放电(ESD)事件时,他们可以保护数字用户线路(DSL)芯片组和线路驱动器。在工作电压范围内拥有小于     

晶体管非线性失真分析

本文从器件物理和结构上提出双极型晶体管非线性失真模型。模型包含8个参量:(1)有效基区展宽效应;(2)发射极电流集边效应;(3)基区电导调制效应;(4)发射结电阻的非线性效应;(5)发射结电容的非线性效应;(6)集电结电容的非线性效应;(7)寄生电容的非线性效应;(8)电流放大系数和雪崩倍增效应与电压的非线性关系。利用Taylor级数展开分析各模型参数,并编制了计算程序,定量计算了互调失真与工作频率、发射极条宽、基区宽度、发射极线电流密度,基区掺杂浓度等重要参数的关系。计算结果与实验结果基本吻合。     

SEBISIT——一种新型抗核辐照高压功率晶体管的研究

本文采用了一种新型结构器件—SEBISIT(Serial Bipolar Static Induction Transistot),成功地改善了高压晶体管的抗核辐射能力。常规高压器件由于具有较大的基区宽度(保证高压工作下基区不穿通)和较厚的外延层(提供足够的击穿电压),故其抗核辐射能力很差。 SEBISIT器件,巧妙地利用了SIT器件的栅的电场屏蔽作用,一方面有效地抑制了高反压下耗尽层向基区的扩展,实现了高压薄基区;另一方面,其屏蔽作用保证了器件有接近于BV_cao为225V.f_T大于400MHZ的加固器件,其中φ_0.5(增益下降至初始值的一半时的辐射剂量)为常规器件的60倍,大大提高了高压器件的加固性能.     

工艺参数对低压TVS器件耐压的影响

目前低压瞬间电压抑制(TVS)二极管工艺参数的研究还不够深入.从深p型(DP)基区杂质浓度、杂质注入能量及基区尺寸控制三个方面探究了工艺条件对低击穿电压的影响.当DP注入剂量小于6.0×1014cm-2时,pn结以雪崩击穿为主,耐压大于6V.DP注入能量在50 keY以下与高浓度n+区复合形成的pn结雪崩击穿耐压大于6V;当控制基区尺寸使n+集电区与DP基区的间距大于1.2 μm时击穿电压保持为7V,但是随着n+与DP基区的间距增加,电流导通路径受到挤压变窄,在相同的反向测试电流下,器件耐压略有提升.通过对单向TVS工艺仿真优化,选择了关键工艺参数,并进行了工程实验,制备了兼具低电容和高抗ESD能力的TVS器件,保证了对主器件实施可靠的保护.     

低开启电压的InGaP/GaAsSb/GaAs双异质结晶体管

采用窄禁带宽度材料GaAsSb作为异质结晶体管的基区材料 ,成功研制出了能有效降低电路工作电压和功率损耗的低开启电压的NPNInGaP/GaAsSb/GaAs双异质结晶体管 (doubleheterojunctionbipolartransistor,DHBT) .器件性能如下 :BE结的正向开启电压 (turn onvoltage)仅为 0 73V ;当IB=1μA/step时 ,直流增益达到了 10 0 ,BVCEO=5～ 6V .通过对基区不同Sb含量器件的比较得到 ,器件的直流特性与基区Sb的含量有关.     

一种单基极引出结构的硅晶体管

为研究单基极薄基区晶体管的特性，设计了一种单侧基极引出结构薄基区的晶体管，在p型SOI衬底上全离子注入实现了基区宽度为80nm的npn纵向结构，基区的平均浓度为1e18cm－3．经过版图设计和工艺流片，在2μm实验工艺线上研制了这种器件．基极采用电压输入，Vbe在1.1V附近，跨导和电流增益都达到峰值，小信号电流增益βac(ΔIc/ΔIb)=2.7，小信号跨导gmac(ΔIc/ΔVbe)=0.45mS，且gmac/gm(Ic/Vbe)比βac/β(Ic/Ib)大得多，跨导比电流增益更能准确地描述器件特性，这种器件更倾向于电压控制型器件，特别适用于数字电路的开发和应用．     

一种机载DC/DC浪涌电流抑制电路的设计

为了满足EMC要求,通常需在机载二次DC/DC的输入端并联大容量电容,导致开机瞬间形成很大的浪涌电流,从而引起系统异常。常规的抑制方法是在输入端串联电感、NTC热敏电阻,或者串联MOS管并简单控制其缓慢开通。但这些方法存在输入电压振荡、高温时抑制失败,或者启动延时长且不能抑制重复快速浪涌等缺点。基于MOS管的密勒效应,设计了一种能够延长MOS管开通上升时间的电路,使电容电压上升速率变缓,从而抑制浪涌电流。仿真及验证结果表明,该电路具有启动延时仅有10 ms、可抑制最高60 Hz的重复快速上电浪涌、上电速率可调等优点。     

电导调制型功率器件用穿通结构的基区优化理论

通过对临界击穿电场近似得出的穿通限制击穿电压的分析 ,提出了电导调制型功率器件用穿通结构的基区优化设计解析理论 :对于电导调制功率器件用的各种穿通结构 ,只要其耐压基区的厚度选择为同衬底浓度突变结击穿时的耗尽层宽度的最佳分割长度 ,即穿通因数 F等于4,就可使外延基区的厚度为最小 .同时 ,该耐压基区的击穿电压为最大 .运用该理论的结果 ,得出了此类应用的基区优化设计公式 ,并将计算结果与一些文献的设计值进行了比较 ,纠正了先前计算的不准确性 .     

提高半导体放电管抗浪涌能力的研究

半导体放电管是新一代抗浪涌保护器件，抗浪涌能力是其最重要的特性参数之一。文中分析了浪涌条件下器件失效的高温物理机制，讨论了器件功耗与传热对抗浪涌能力的影响，指出采用多元胞结构可降低由热量集中造成的最高结温，从而提高了器件的抗浪涌能力。     

玻璃钝化技术对半导体放电管抗浪涌能力的影响

半导体放电管是新一代抗浪涌保护器件，极问电容是其应用到高频环境下的一个限制因素。文章从半导体放电管的基本结构出发，介绍了用玻璃钝化技术去除放电管侧壁电容的方法。理论分析表明，在没有采用玻璃钝化技术时，流过放电管结底部的电流大于流过其侧壁的电流，因此，采用玻璃钝化技术对半导体放电管的抗浪涌能力影响不大。     

Partial-SOI isolation structure for reduced bipolar transistorparasitics

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure     

Implementing the TIL Concept in high-power GTO's

This work reports the results obtained in the implementation of the novel two interdigitation level (TIL) gate-cathode configuration in high-voltage (2000 V), high-current (600 A), gate turn-off (GTO) thyristors. It is shown that the implementation of the TIL concept in high-power GTO's, while relaxing the trade-off between the doping/ width of the p base and the main electrical parameters, offers a fair balance between manufacturability ease/cost effectiveness and overall device performance. A distinct benefit obtained through the implementation of the TIL pattern in high-power GTO's is expressed by the ability of devices with an active area of only 1.7 cm²to safely switch off an anode current of 600 A with a practically usable operational turn-off gain Goffof 5-8. The low on-state voltage drop of gold-doped, high-power TIL GTO's is accompanied by a high nonrepetitive surge current capability. The trial devices possess a good latching/turn-on sensitivity accompanied by an immunity to noise (high dV/dt capability).     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

多电平单元串联电压源型变频器高压电源瞬时失电连续运行研究

高压变频调速系统现场应用复杂，工艺多样。在重要的大型工业系统中，高压电源系统有双备用，紧急互投等功能，当变频器对大功率的电机供电时，如果高压电源进行切换，将出现0．1S～1．5s左右的失电间隔，要求变频器在失电间隔中能正常工作，且转速波动较小，达到系统在失电期间不出现剧烈振荡。对于多电平单元串联电压源型变频器，当通过对功率单元电容值的加大，PWM输出占空比减小的方法提高失电连续运行性能，其效果均不理想。在经过大量论证后，采用特殊的DSP控制逻辑，并利用旋转系统中的飞轮动能转换，取得实现变频器在高压瞬时失电时保持稳定运行。     

Small-signal analysis of the gate-controlled diode

This paper describes the small signal behavior of MOS gate-controlled diodes. An expression for the capacitance of this device is developed from basic device physics equations. Computer calculations are compared with measured data and the model is seen to predict both the frequency and voltage dependence of the capacitance. The development of this model was made possible through the careful decomposition of teh basic MOS equations into time dependent and static parts.     

一种有机薄膜器件的制备及电存储特性

研究了一种金属/有机物/金属夹层结构有机薄膜器件的可逆电双稳特性.器件的阳极和阴极分别为真空热蒸发沉积的Ag和Al薄膜,中间介质层为真空热蒸发沉积的2-(hexahydropyrimidin-2-ylidene)-malononitrile(HPYM)有机薄膜.器件起始状态为非导通态,在大气环境下,可用正、反向电场进行信号的写入和擦除,表现为极性记忆特性.通过自然氧化的方法在底电极Al表面形成一层Al2O3薄膜层后,可使器件在不同的正向电压脉冲作用下达到不同的导电态,具有一定的多重态存储特性.同时,研究了不同的电极组合对器件电性能的影响,并通过紫外-可见吸收光谱以及喇曼光谱对器件界面进行表征.     

A circuit simulation model for high-frequency power MOSFETs

A circuit simulation model suitable for modeling the static and dynamic switching characteristics of high-frequency power MOSFETs is reported. The model parameters were obtained from physical device layout, silicon doping, and measured electrical characteristics of power MOSFETs. Accurate voltage dependencies of the interelectrode capacitances were obtained from extensive two-dimensional device simulations. The voltage dependence of gate-drain capacitance was modeled using an analytic expression. The measured static current-voltage and transient-switching responses under resistive switching conditions are in excellent agreement with simulation results obtained from SPICE. The MOSFET subcircuit model was used to accurately predict the performance of a series-parallel resonant DC-DC converter using a multilevel system simulator