Random telegraph signals in deep submicron n-MOSFET's

Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO₂ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel     

Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.     

Power dissipation analysis and optimization of deep submicron CMOSdigital circuits

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and η, which reflects the drain induced barrier lowering, are also addressed     

动态电子束探针检测技术在亚微米和深亚微米IC失效分析中的应用研究

对扫描电子显微镜静态/动态/电容耦合电压衬度像、电子束感生电流像、电阻衬度像在亚微米和深亚微米超大规模集成电路中的成像方法和成像特点进行了研究,对各种分析技术在失效分析中的应用进行了深入的探讨,为电子束探针检测技术在亚微米和深亚微米集成电路故障定位和失效机理分析中的应用提供了理论基础和实践依据.     

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I_b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons     

Reliability challenges for deep submicron interconnects

Deep submicron interconnects (leads, contacts and vias) are rapidly becoming one of the major reliability challenges as ULSI devices continue to be scaled. With 0.5um feature sizes now common, trying to balance reliability and performance requirements is increasing difficult as we move toward <0.25um. By the end of the decade, current density in metal leads will be >0.5 Ma/cm2 and single 0.20–0.25um contacts and vias will be required to safely carry 1–2ma of current. This increases electromigration concerns, with vias generally now being the weakest link in a reliable ULSI multilevel-metal system.     

Channel noise modeling of deep submicron MOSFETs

This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.     

Modeling the wiring of deep submicron ICs

The semiconductor industry has fuelled the enormous growth of the electronics industry with an unending flow of even better, faster, cheaper chips. These chip improvements, in turn, have been stoked by steady progress in semiconductor process technology, which, as Moore's law predicts, doubles IC transistor counts every 18 months. Supporting this progress is the infrastructure provided by design tools, which today, however, comes up short against the process advances crucial to tomorrow's chips. Why? Because present design tools and methodologies presuppose that chip performance is determined by the transistor. That supposition may have been true a few years ago, but no more. Chip performance now depends on the interconnect. The new significance of interconnect performance is driving changes throughout the logic design flow because logic synthesis engines and other tools assume that timing can be predicted before the physical layout is done. But pre-layout and post-layout timing values no longer converge, and design tools must evolve to match this change in process technology. The first step is for vendors to create tools that accurately predict the performance of designs in this interconnect-dominated technology. The author discusses the importance of timing, 2D and 3D modelling of the interconnects, and deep submicron effects     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

辐射对深亚微米NMOS器件热载流子效应的影响

We investigate how F exposure impacts the hot-carrier degradation in deep submicron NMOSFET with different technologies and device geometries for the first time. The results show that hot-carrier degradations on irradiated devices are greater than those without irradiation, especially for narrow channel device. The reason is attributed to charge traps in STI, which then induce different electric field and impact ionization rates during hotcarrier stress.     

Prognostic methodology for deep submicron semiconductor failuremodes

Semiconductor reliability issues are beginning to emerge as a major impediment to long term reliability of critical systems such as Internet routers, ATM machines, and Automotive/Aerospace fly-by-wire systems. Semiconductors have certain defined failure modes that can contribute to end-of life failures. These modes include time-dependent dielectric breakdown of the gate oxide (TDDB), hot carrier damage, and metal migration. All of these common failure modes are far worse at geometries below 0.25 μm. Fortunately, there are methods proposed that counteract these common failure modes. This paper surveys the problems involved, and recommends a methodology for the inclusion of pre-calibrated prognostic cells that can be co-located with a host circuit to provide an “early-warning” of a system failure, so that appropriate corrective action can be taken     

Fabrication of submicron photon sieve using E-beam lithography and X-ray lithography

In this paper, a new hybrid method to fabricate submicron photon sieve is proposed, where the E-beam lithography and the X-ray lithography are used. It is found that 2.8 μm thickness of the polyimide film, 400 nm thickness of the ZEP-520 and 280 μC/cm² exposure dose are good for E-beam lithography, while 500 nm thickness of the PMMA and 30 s developing time are good for X-ray lithography. We have successfully fabricated the photon sieve with these parameters (the diameter of photon sieve: 250 μm, the focal length: 150 μm, the diameter of the outmost pinhole: 420 nm). Some key techniques of this method are analyzed respectively, and the error analysis are done at the end of this paper. It provides a direction of nanoscale optical element fabrication with higher resolution and lower cost.     

A bus energy model for deep submicron technology

We present a comprehensive mathematical analysis of the energy dissipation in deep submicron technology buses. The energy estimation is based on an elaborate bus model that includes distributed and lumped parasitic elements that appear as technology scales. The energy drawn from the power supply during the transition of the bus is evaluated in a closed form. The notion of the transition activity of an individual line is generalized to that of the transition activity matrix of the bus. The transition activity matrix is used for statistical estimation of the power dissipation in deep submicron technology buses.     

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25°C to 125°C) of the four components of off-state drain leakage (I_off ) (i.e. subthreshold leakage (I_sub), gate edge-direct-tunneling leakage (I_EDT), gate-induced drain-leakage (I_GIDL), and bulk band-to-band-tunneling leakage (I_B-BTBT)). In addition, the high temperature characteristics of I_off with reverse body bias (V_B) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 μm, 0.15 μm, and 0.13 μm). Experiments show that the optimum V_B, which minimizes I_off, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I_B-BTBT and I_GIDL by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I_G-on) and I_EDT specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I_SB) is also analyzed     

Characterization and modeling of parasitic emission in deep submicron CMOS

This paper presents a study of the parasitic emissions of a 0.18-/spl mu/m CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.     

深亚微米PDSOI nMOSFETs的短沟道效应

基于中国科学院微电子所开发的0.35µmSOI工艺制备了深亚微米PDSOI nMOSFET。根据阈值电压依赖沟道长度的测试结果阐述了决定PDSOI nMOSFET 短沟道效应的机理。研究了体偏置、漏偏置以及温度和体接触对PDSOI nMOSFET 短沟道效应的影响,发现短沟道效应依赖于体偏置、漏偏置以及体接触。浮体器件比有体接触结构的器件的反短沟道效应更严重,器件在低体偏和高漏偏下会表现出更明显的短沟道效应。     

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOl devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.     

Intrinsic leakage in deep submicron CMOS ICs-measurement-based testsolutions

The high leakage current in deep submicron, short-channel transistors can increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I_DDQ)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I_DDQ and ICs maximum operating frequency (F_max) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I_DDQ along with F_max can be effectively used to screen defects in high performance, low V_T (transistor threshold voltage) CMOS ICs     

激光定位深亚微米CMOS SRAM单粒子翻转敏感区

The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18/zm CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.     

An analytical thermal noise model of deep submicron MOSFET's

An analytical model for circuit simulation to describe the channel thermal noise in MOSFET's for all channel length down to deep submicron is presented and verified by measurements. Contrary to the thermal equilibrium assumption, this model includes the influence of the increasing electrical field with downscaling on the channel carrier (electron, hole) equivalent noise temperature. If not taken into account, simulation errors of up to 100% and more in the thermal noise of half micron transistors and below occur