The effects of process conditions and substrate on copper MOCVD using liquid injection of (hfac)Cu(vtmos)

Copper MOCVD (metalorganic chemical vapor deposition) using liquid injection for effective delivery of the (hfac)Cu(vtmos) [1,1,1,5,5,5-hexafluoro-2,4-pentadionato(vinyltrimethoxysilane) copper(I)] precursor has been performed to clarify growth behavior of copper films onto TiN, <100> Si, and Si₃N₄ substrates. Especially, we have studied the influences of process conditions and the substrate on growth rates, impurities, microstructures, and electrical characteristics of copper films. As the reactor pressure was increased, the growth rate was governed by a pick-up rate of (hfac)Cu(vtmos) in the vaporizer. The apparent activation energy for copper growth over the surface-reaction controlled regime from 155°C to 225°C was in the range 12.7–32.5 kcal/mol depending upon the substrate type. It revealed that H₂ addition at 225°C substrate temperature brought about a maximum increase of about 25% in the growth rate compared to pure Ar as the carrier gas. At moderate deposition temperatures, the degree of a <111> preferred orientation for the deposit was higher on the sequence of <Cu/Si<Cu/TiN<Cu/Si₃N₄. The relative impurity content within the deposit was in the range 1.1 to 1.8 at.%. The electrical resistivity for the Cu films on TiN illustrated three regions of the variation according to the substrate temperature, so the deposit at 165°C had the optimum resistivity value. However, the coarsened microstructures of Cu on TiN prepared above 275°C gave rise to higher electrical resistivities compared to those on Si and Si₃N₄ substrates.     

Laser-assisted via hole metallization in PCB materials

A novel via hole metallization method is presented, where the vias are drilled in polyimide/copper (PI/Cu) flexible printed circuit boards (PCBs) using KrF excimer pulses, and then pre-metallized using a scanned Ar⁺ laser. In the premetallization step, a thin (20–50 nm) and narrow (2–10 μm) palladium layer is deposited on the polyimide-covered side of the PCB and on the wall of the vias using the laser-induced chemical liquid-phase deposition method. After the pretreatment, the Pd covered holes are immersed into a Cu electroless plating bath. Plated copper vertical and horizontal interconnects are analyzed by optical microscopy, focused ion beam, profilometry and resistivity measurements. The results show that the copper deposits formed on the pre-metallized surface of PCBs have high chemical purity, excellent adhesion and almost bulk conductivity, but, so far, due to unclear reasons, high through hole resistance.     

Electroless Ni/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones

Wafer bumping technology using an electroless Ni/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni/Au bump. This study measures the shear forces on Ni/Au bumps prepared in different ways, showing that the suitable pretreatment protocol for electroless Ni plating on Cu pads is “acid dip followed by Pd activation” rather than the conventional progression of “acid-dip, microetching, and Pd activation.” The interface between the Cu pad and the Ni/Au bump is studied using various surface analysis methods. The homogeneous distribution of catalytic Pd on the Cu pad is first validated. The flip chip package structure is designed, assembled, and tested for reliability. The successful flip chip bonding in the CIS package is characterized in terms of the cross-sectional structure in which the anisotropic conductive film (ACF) particles are deformed to about 1.5 μm in diameter. The experimental results suggest that electroless Ni/Au can be applied to the flip chip type CIS package using Cu patterned wafers for high mega pixel applications.     

Fabrication of potential NiMoP diffusion barrier/seed layers for Cu interconnects via electroless deposition

Potential NiMoP barrier/seed layers for Cu interconnects have been successfully formed by electroless deposition on SiO₂. Four different wet processes were attempted to activate the surface before electroless deposition. Material properties including the crystal structure, deposition rate, composition, and electrical resistivity of NiMoP layers were investigated by atomic force microscopy (AFM), scanning electron microscopy (SEM), Auger electron spectroscopy, x-ray diffraction (XRD), four-point probe, and surface profilometry (Alpha-step). In this study, different compositions of NiMoP films have been obtained. Ni₈₉Mo₂P₉ with nanocrystalline structure has the highest resistivity due to enriched P content, while Ni₈₈Mo₉P₃ has the lowest value among the compositions considered in this study. The seed layer and the barrier layer functions of NiMoP were verified by direct Cu electrodeposition and secondary ion mass spectroscopy (SIMS).     

Electroless deposition of Co(W) thin films

Thin films of cobalt that contain small amounts of tungsten [Co(W)] were deposited by the electroless process. Those films do not contain either phosphorus or boron which are included in most electroless cobalt films processes. The deposition bath for Co(W) thin films include Co ions, tungstate ions as a source for tungsten, di-methyl-amine-borane (DMAB) complex as a reducing agent, ammonium hydrate as a complexing agent, acetic acid for buffering and surfactants. Co(W) layers were deposited on two types of seed layers: (a) thin sputtered cobalt or copper films on 100 nm SiO₂/Si and (b) bare silicon wafers activated by an aqueous Pd/PdCl₂ solution. The deposited layer thickness range was 40–1000 nm with deposition rate at 90 °C and pH 9 of 7 nm/s for both Pd activated Si and sputtered Co seed, and 5 nm/s for the sputtered Cu seed. Lowering the temperature to 70 °C lowered the deposition rate to 0.7 nm/s for the Pd activated Si. The deposited layers were bright coloured, uniform, and with low defect density under visual inspection. The thin films composition was found to be Cobalt with 3–4 at.% tungsten for all types of seed layers. The Co(W) thin films specific resistivity was in the range of 60–90 μΩ cm. Finally we present the thin film morphology as it was characterized using atomic force microscopy and scanning electron microscopy.     

Structural and Passivative Behaviors of Cu(In) Thin Film

This investigation prepares a low-resistivity and self-passivated Cu(In) thin film. The dissociation behaviors of dilute Cu-alloy thin films, containing 1.5–5at.%In, were prepared on glass substrates by a cosputter deposition, and were subsequently annealed in the temperature range of 200–600 °C for 10–30 min. Thus, self-passivated Cu thin films in the form In₂O₃/Cu/SiO₂ were obtained by annealing Cu(In) alloy films at an elevated temperature. Structural analysis indicated that only strong copper diffraction peaks were detected from the as-deposited film, and an In₂O₃ phase was formed on the surface of the film by annealing the film at an elevated temperature under oxygen ambient. The formation of In₂O₃/Cu/SiO₂ improved the resistivity, adhesion to SiO₂, and passivative capability of the studied film. A dramatic reduction in the resistivity of the film occurred at 500 °C, and was considered to be associated with preferential indium segregation during annealing, yielding a low resistivity below 2.92 μΩcm. The results of this study can be potentially exploited in the application of thin-film transistor–liquid crystal display gate electrodes and copper metallization in integrated circuits.     

Growth of High-Density Self-Aligned Carbon Nanotubes and Nanofibers Using Palladium Catalyst

In this paper we demonstrate vertical self-aligned growth of carbon nanotubes (CNT) and carbon nanofibers (CNF) using 1 nm of Pd as the catalyst material. Results were compared with those obtained using traditional catalysts (Co, Fe, and Ni). Pd is of interest as it has been demonstrated to be an excellent material for electrical contact to nanotubes. CNT were grown using plasma-enhanced chemical vapor deposition (PECVD) at 450°C to 500°C and using atmospheric-pressure chemical vapor deposition (APCVD) between 450°C and 640°C. The results were investigated by scanning electron microscopy (SEM), transmission electron microscopy (TEM), and Raman spectroscopy. High-density (10¹¹ cm⁻² to 10¹² cm⁻²) self-aligned CNT growth was obtained using APCVD and Pd as the catalyst, while Co and Fe resulted in random growth. TEM revealed that the CNT grown by Pd with PECVD form large bundles of tubes, while Ni forms large-diameter CNF. It was found that the CNT grown using Pd or Ni are of low quality compared with those grown by Co and Fe.     

Growth of an intermetallic compound layer with Sn-3.5Ag-5Bi on Cu and Ni-P/Cu during aging treatment

Growth kinetics of intermetallic compound (IMC) layers formed between the Sn-3.5Ag-5Bi solder and the Cu and electroless Ni-P substrates were investigated at temperatures ranging from 70°C to 200°C for 0–60 days. With the solder joints between the Sn-Ag-Bi solder and Cu substrates, the IMC layer consisted of two phases: the Cu₆Sn₅ (η phase) adjacent to the solder and the Cu₃Sn (ε phase) adjacent to the Cu substrate. In the case of the electroless Ni-P substrate, the IMC formed at the interface was mainly Ni₃Sn₄, and a P-rich Ni (Ni₃P) layer was also observed as a by-product of the Ni-Sn reaction, which was between the Ni₃Sn₄ IMC and the electroless Ni-P deposit layer. With all the intermetallic layers, time exponent (n) was approximately 0.5, suggesting a diffusion-controlled mechanism over the temperature range studied. The interface between electroless Ni-P and Ni₃P was planar, and the time exponent for the Ni₃P layer growth was also 0.5. The Ni₃P layer thickness reached about 2.5 μm after 60 days of aging at 170°C. The activation energies for the growth of the total Cu-Sn compound layer (Cu₆Sn₅ + Cu₃Sn) and the Ni₃Sn₄ IMC were 88.6 kJ/mol and 52.85 kJ/mol, respectively.     

Thermal performance of sputtered insoluble Cu(W) films for advanced barrierless metallization

The thermal performance of sputtered Cu films with dilute insoluble W (1.3 at.%) on barrierless Si substrates has been studied, using the analyses of focused ion beam, x-ray diffraction, and electrical resistivity measurement. The role of the Cu(W) film as a seed layer has been confirmed based on the thermal performance evaluations in both thermal cycling and isothermal annealing at various temperatures. The electrical resistivity of ∼1.8 μΩ-cm for Cu/Cu(W) film is obtained after thermal annealing at 400°C. Because of the good thermal stability, the Cu(W) seed layer is also considered to act as a diffusion buffer and is stable up to 490°C for the barrierless Si scheme. The results indicate that the Cu/Cu(W) scheme has potential in advanced barrierless metallization applications.     

A rapid growth of aligned carbon nanotube films and high-aspect-ratio arrays

The remarkable properties of carbon nanotubes (CNTs) make them attractive for microelectronic applications, especially for interconnects and nanoscale devices. In this paper, we report an efficient process to grow well-aligned CNT films and high-aspect-ratio CNT arrays with very high area distribution density (>1600 μm⁻²). Chemical vapor deposition (CVD) was invoked to deposit highly aligned CNTs on Al₂O₃/Fe coated silicon substrates of several square centimeter area using ethylene as the carbon source, and argon and hydrogen as carrier gases. The nanotubes grew at a high rate of ∼100 μm/min. for nanotube films at 800°C, while the nanotube arrays grew at ∼140 μm/min. even at 750°C, due to the base growth mode. The CNTs were characterized by transmission electron microscopy (TEM), scanning electron microscopy (SEM), and x-ray photoelectron spectroscopy (XPS). The results demonstrated that the CNTs are of high purity and form densely aligned arrays with controllable size and height. The as-grown CNT structures have considerable potential for thermal management and electrical interconnects for microelectronic devices.     

High conductivity copper-boron alloys obtained by low temperature annealing

The electrical behavior during annealing of copper films with a nominal concentration of 2 at.% boron has been investigated. The evolution of the resistivity of the film was monitored using an in situ technique, in which the film was rampannealed at constant ramp rates. At temperature of 150–200°C, the resistivity of the Cu(B) undergoes a first drop. This is followed by one or two such drops in resistivity, so that after completion of a ramp-anneal from 50°C to 750°C, the room temperature resistivity decreases from the initial value of 13 μΩ cm to 2.1 μΩcm, close to that of bulk copper. Isothermal annealing of the film also leads to substantial decreases in resistivity, from 13 μΩcm to 3 μΩ cm after annealing at 350°C for 8 h and to 2.5 μΩ cm at 400°C for 4 h. These results show that a dramatic reduction in resistivity of Cu(B) alloys takes place at temperatures below 400°C, suggesting possible applications for silicon device interconnections.     

Effect of Pd Thickness on the Interfacial Reaction and Shear Strength in Solder Joints Between Sn-3.0Ag-0.5Cu Solder and Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) Surface Finish

Intermetallic compound formation at the interface between Sn-3.0Ag-0.5Cu (SAC) solders and electroless nickel/electroless palladium/immersion gold (ENEPIG) surface finish and the mechanical strength of the solder joints were investigated at various Pd thicknesses (0 μm to 0.5 μm). The solder joints were fabricated on the ENEPIG surface finish with SAC solder via reflow soldering under various conditions. The (Cu,Ni)₆Sn₅ phase formed at the SAC/ENEPIG interface after reflow in all samples. When samples were reflowed at 260°C for 5 s, only (Cu,Ni)₆Sn₅ was observed at the solder interfaces in samples with Pd thicknesses of 0.05 μm or less. However, the (Pd,Ni)Sn₄ phase formed on (Cu,Ni)₆Sn₅ when the Pd thickness increased to 0.1 μm or greater. A thick and continuous (Pd,Ni)Sn₄ layer formed over the (Cu,Ni)₆Sn₅ layer, especially when the Pd thickness was 0.3 μm or greater. High-speed ball shear test results showed that the interfacial strengths of the SAC/ENEPIG solder joints decreased under high strain rate due to weak interfacial fracture between (Pd,Ni)Sn₄ and (Cu,Ni)₆Sn₅ interfaces when the Pd thickness was greater than 0.3 μm. In the samples reflowed at 260°C for 20 s, only (Cu,Ni)₆Sn₅ formed at the solder interfaces and the (Pd,Ni)Sn₄ phase was not observed in the solder interfaces, regardless of Pd thickness. The shear strength of the SAC/ENIG solder joints was the lowest of the joints, and the mechanical strength of the SAC/ENEPIG solder joints was enhanced as the Pd thickness increased to 0.1 μm and maintained a nearly constant value when the Pd thickness was greater than 0.1 μm. No adverse effect on the shear strength values was observed due to the interfacial fracture between (Pd,Ni)Sn₄ and (Cu,Ni)₆Sn₅ since the (Pd,Ni)Sn₄ phase was already separated from the (Cu,Ni)₆Sn₅ interface. These results indicate that the interfacial microstructures and mechanical strength of solder joints strongly depend on the Pd thickness and reflow conditions.     

Manufacturing of Cu/electroless nickel/Sn-Pb flip chip solder bumps

A process for manufacturing Cu/electroless Ni/Sn-Pb solder bump is discussed in this paper. An attempt to replace zincation with a Cu film as an active layer for the electroless Ni (EN) deposition on Al electrode on Si wafer is presented. Cu/electroless Ni is applied as under bump metallurgy (UBM) for solder bump. The Cu film required repeated etches with nitric acid along with activation to achieve a satisfactory EN deposit. Fluxes incorporating rosin and succinic acid were investigated for wetting kinetics and reflow effectiveness of the electroplated solder bump. The solder plating current density and the reflow condition for achieving solder bumps with uniform bump height were described. The Cu/EN/Sn-Pb solder system was found to be successfully produced on Al terminal in this study that avoids using zincating process     

Cover Picture: Formation of Metal Nano‐ and Micropatterns on Self‐Assembled Monolayers by Pulsed Laser Deposition Through Nanostencils and Electroless Deposition (Adv. Funct. Mater. 10/2006)

The cover illustrates two‐step fabrication of metal micro‐ and nanostructures on self‐assembled monolayers (SAMs) by pulsed laser deposition and electroless deposition. Metal–SAM–metal junctions are a key component of molecular electronic devices. Pt was deposited in a micropattern by pulsed laser deposition through a stencil. XPS maps show how the Pt pattern is developed into a Cu pattern using electroless deposition as reported by Ravoo, Brugger, Reinhoudt, Blank, and co‐workers on p. 1337. The Cu pattern can also be observed by optical microscopy (background). Patterns of noble‐metal structures on top of self‐assembled monolayers (SAMs) on Au and SiO₂ substrates have been prepared following two approaches. The first approach consists of pulsed laser deposition (PLD) of Pt, Pd, Au, or Cu through nano‐ and microstencils. In the second approach, noble‐metal cluster patterns deposited through nano‐ and microstencils are used as catalysts for selective electroless deposition (ELD) of Cu. Cu structures are grown on SAMs on both Au and SiO₂ substrates and are subsequently analyzed using X‐ray photoelectron spectroscopy element mapping, atomic force microscopy, and optical microscopy. The combination of PLD through stencils on SAMs followed by ELD is a new method for the creation of (sub)‐micrometer‐sized metal structures on top of SAMs. This method minimizes the gas‐phase deposition step, which is often responsible for damage to, or electrical shorts through, the SAM.     

Effect of crystallinity and thickness on the diffusion barrier behavior of electroless nickel deposit between Cu and solder

The crystallinity of electroless nickel deposit was manipulated by applying bath stabilizer including lead acetate and thiourea. A crystalline deposit and a higher deposition rate of electroless nickel were achieved with thiourea than with lead acetate. The effect of crystallinity on the diffusion barrier performance of the electroless nickel deposit was studied between solder and Cu deposit. The thickness of the electroless nickel deposit investigated includes 1, 3, and 5 /spl mu/m. It was found that both crystalline and amorphous deposits perform similarly in barrier performance except when the thickness of the deposit is as thin as 1 /spl mu/m. Cross sectional elemental analysis results indicate that a 3 /spl mu/m thickness deposit can withstand ten times of reflow without counter diffusion between Sn and Cu, although Ni-Sn intermetallic compounds were formed. The 3 /spl mu/m thickness is also adequate for barrier function after 1000 hours of aging at 150/spl deg/C.     

Effect of Pd Surface Roughness on the Bonding Process and High Temperature Reliability of Au Ball Bonds

A 0.3-μm-thick electrolytic Pd layer was plated on 1 μm of electroless Ni on 1 mm-thick polished and roughened Cu substrates with roughness values (R _a) of 0.08 μm and 0.5 μm, respectively. The rough substrates were produced with sand-blasting. Au wire bonding on the Ni/Pd surface was optimized, and the electrical reliability was investigated under a high temperature storage test (HTST) during 800 h at 250°C by measuring the ball bond contact resistance, R _c. The average value of R _c of optimized ball bonds on the rough substrate was 1.96 mΩ which was about 40.0% higher than that on the smooth substrate. The initial bondability increased for the rougher surface, so that only half of the original ultrasonic level was required, but the reliability was not affected by surface roughness. For both substrate types, HTST caused bond healing, reducing the average R _c by about 21% and 27%, respectively. Au diffusion into the Pd layer was observed in scanning transmission electron microscopy/ energy dispersive spectroscopy (STEM–EDS) line-scan analysis after HTST. It is considered that diffusion of Au or interdiffusion between Au and Pd can provide chemically strong bonding during HTST. This is supported by the R _c decrease measured as the aging time increased. Cu migration was indicated in the STEM–EDS analysis, but its effect on reliability can be ignored. Au and Pd tend to form a complete solid solution at the interface and can provide reliable interconnection for high temperature (250°C) applications.     

Interfacial evolution and bond reliability in thermosonic Pd coated Cu wire bonding on aluminum metallization: Effect of palladium distribution

In this paper, the growth kinetics of Cu–Al intermetallic compounds formed during isothermal annealing of Pd–Cu wire bonds with different palladium distribution at 175 °C are investigated by electron microscopy and compared to bare Cu wire bonds. Transmission electron microscopy (TEM) was used to provide high resolution imaging of the Cu–Al IMCs in the as-bonded state and TEM-EDX used to analyze the concentrations of Pd at the bond interface in the as-bonded state. Cu–Al IMCs were found to grow thicker with increasing annealing duration. The growth kinetics of the Cu–Al IMCs were correlated with the diffusion process during thermal annealing. The IMC thickness for Pd–Cu wire bonds with Pd at the bond interface was found to be thinner as compared to that for Pd–Cu wire bonds with no Pd at the bond interface. Thus, the presence of palladium at the bond interface has slowed down the IMC growth. Nano-voids were found in the Pd–Cu wire bonds with Pd at the bond interface, but not in the Pd–Cu wire bonds with no Pd at the bond interface. The IMC growth rate for the Pd–Cu bonds with no Pd was found to be close to that for bare Cu for the initial annealing durations. Corresponding bond pull testing showed that Pd–Cu wire bonds containing Pd have best preserved the bond strength after 168 h aging at 175 °C due to the beneficial presence of Pd.     

Magnetic Silver-Coated Ferrite Nanoparticles and Their Application in Thick Films

Magnetic silver-coated ferrite nanoparticles with 39.8% weight gain (relative to ferrite nanopowder coated by a silver layer) were synthesized by electroless deposition of silver on ferrite nanopowder. The mechanism of the electroless deposition was explored in terms of pretreatment, sensitization, activation, and the reduction of silver–ammonia complexes. Experiments showed that the optimal deposition conditions were a temperature of 50°C, pH value of 10 to 12, duration of 65 min with ethanol plus polyethylene glycol as additives, and ultrasonic vibration as a method of dispersing the nanoparticles. From transmission electron microscopy (TEM) images, it was observed that as-synthesized nanoparticles had a core–shell structure with a particle size of 35 nm to 90 nm and a shell thickness of 5 nm to 20 nm. X-ray diffraction (XRD) analysis confirmed that only ferrite and metallic silver were present in the product. Electrical resistance and magnetic hysteresis measurements demonstrated that the nanoparticles were both electrically conductive (volume electrical resistivity on the order of 10⁻⁴ Ω cm to 10⁻³ Ω cm when compressed to pressure of 2 × 10 ⁶ Pa) and possessed ferrimagnetic properties. After a thick-film paste, obtained with the nanoparticles as the functional phase, was directly written and sintered, scanning electron microscopy (SEM) analysis and electrical resistance measurements of conductive lines in the acquired array pattern showed that an electrically conductive network with some defects and cavities was formed, with a volume electrical resistivity of 1 × 10⁻⁴ Ω cm to 1 × 10⁻³ Ω cm.     

Thermal Stability Study of Cu(MoN<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>) Seed Layer on Barrierless Si

This study reports the good thermal stability of a sputtered Cu(MoN _x ) seed layer on a barrierless Si substrate. A Cu film with a small amount of MoN _x was deposited by reactive co-sputtering of Cu and Mo in an Ar/N₂ gas mixture. After annealing at 560°C for 1 h, no copper silicide formation was observed at the interface of Cu and Si. Leakage current and resistivity evaluations reveal the good thermal reliability of Cu with a dilute amount of MoN _x at temperatures up to 560°C, suggesting its potential application in advanced barrierless metallization. The thermal performance of Cu(MoN _x ) as a seed layer was evaluated when pure Cu is deposited on top. X-ray diffraction, focused ion beam microscopy, and transmission electron microscopy results confirm the presence of an ∼10-nm-thick reaction layer formed at the seed layer/Si interface after annealing at 630°C for 1 h. Although the exact composition and structure of this reaction layer could not be unambiguously identified due to trace amounts of Mo and N, this reaction layer protects Cu from a detrimental reaction with Si. The Cu(MoN _x ) seed layer is thus considered to act as a diffusion buffer with stability up to 630°C for the barrierless Si scheme. An electrical resistivity of 2.5 μΩ cm was obtained for the Cu/Cu(MoN _x ) scheme after annealing at 630°C.     

Temperature and duration effects on microstructure evolution during copper wafer bonding

Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for 60 min achieve the same excellent bonding quality.