Comparison of wavelet families for texture classification by using wavelet packet entropy adaptive network based fuzzy inference system

Recently, significant of the robust texture image classification has increased. The texture image classification is used for many areas such as medicine image processing, radar image processing, etc. In this study, a new method for invariant pixel regions texture image classification is presented. Wavelet packet entropy adaptive network based fuzzy inference system (WPEANFIS) was developed for classification of the twenty 512 × 512 texture images obtained from Brodatz image album. There, sixty 32 × 32 image regions were randomly selected (overlapping or non-overlapping) from each of these 20 images. Thirty of these image regions and other 30 of these image regions are used for training and testing processing of the WPEANFIS, respectively. In this application study, Daubechies, biorthogonal, coiflets, and symlets wavelet families were used for wavelet packet transform part of the WPEANFIS algorithm, respectively. In this way, effects to correct texture classification performance of these wavelet families were compared. Efficiency of WPEANFIS developed method was tested and a mean %93.12 recognition success was obtained.     

TexNN: Fast Texture Encoding Using Neural Networks

We present a novel deep learning‐based method for fast encoding of textures into current texture compression formats. Our approach uses state‐of‐the‐art neural network methods to compute the appropriate encoding configurations for fast compression. A key bottleneck in the current encoding algorithms is the search step, and we reduce that computation to a classification problem. We use a trained neural network approximation to quickly compute the encoding configuration for a given texture. We have evaluated our approach for compressing the textures for the widely used adaptive scalable texture compression format and evaluate the performance for different block sizes corresponding to 4 × 4, 6 × 6 and 8 × 8. Overall, our method (TexNN) speeds up the encoding computation up to an order of magnitude compared to prior compression algorithms with very little or no loss in the visual quality.     

Sub-pattern texture recognition using intelligent focal-plane imaging sensor of small window-size

In this paper we demonstrate how to use statistical evaluation for texture recognition in the case of window-size of the imaging focal-plane sensor being smaller than the pattern of the texture. The evaluation method is similar to the sub-pixel pattern recognition developed by the first author. We have reported in an earlier publication on the development of a new single-chip texture classifier smart-sensor system, whose main part is a cellular nonlinear network (CNN) VLSI chip. This architecture is very fast but it has a limited window-size. Now we show that this architecture can effectively recognize textures of periodicity larger than the window-size. As a result, we recognized 15 Brodatz-textures by using a 20 × 22 CNN chip with a 0.4% error-rate.     

A hardware architecture for real-time image compression using a searchless fractal image coding method

In this paper we present a novel hardware architecture for real-time image compression implementing a fast, searchless iterated function system (SIFS) fractal coding method. In the proposed method and corresponding hardware architecture, domain blocks are fixed to a spatially neighboring area of range blocks in a manner similar to that given by Furao and Hasegawa. A quadtree structure, covering from 32 × 32 blocks down to 2 × 2 blocks, and even to single pixels, is used for partitioning. Coding of 2 × 2 blocks and single pixels is unique among current fractal coders. The hardware architecture contains units for domain construction, zig-zag transforms, range and domain mean computation, and a parallel domain-range match capable of concurrently generating a fractal code for all quadtree levels. With this efficient, parallel hardware architecture, the fractal encoding speed is improved dramatically. Additionally, attained compression performance remains comparable to traditional search-based and other searchless methods. Experimental results, with the proposed hardware architecture implemented on an Altera APEX20K FPGA, show that the fractal encoder can encode a 512 × 512 × 8 image in approximately 8.36 ms operating at 32.05 MHz. Therefore, this architecture is seen as a feasible solution to real-time fractal image compression.

SMAC: A VLSI Architecture for Scene Matching

Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. In this paper, we describe an efficient architecture for scene matching called SMAC (Scene Matching ArChitecture). The architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining. Such an architecture can be used to compute the exhaustive search task of hierarchical scene matching, a technique used to reduce the amount of computations involved in scene matching applications. A prototype very large scale integration (VLSI) chip implementing a scaled down version of the proposed architecture has been designed and built. The prototype chip has been tested to be fully functional at a frequency of 50 MHz with a clock cycle of 20 ns. Based on the prototype design, it is estimated that the proposed architecture can process a 512 × 512 image with an 128 × 128 size template in about 15.36 μs, which corresponds to a rate of 65K frames per second.     

The Use of Boolean Model for Texture Analysis of Grey Images

We generalize here the use of the 1D Boolean model for the analysis of grey level textures. Each grey image is first split into eight binary images using different criteria. Each of these binary images is separately analysed with the help of the 1D Boolean model and features are extracted from it. The final grey texture recognition is performed on the basis of these features using several classification criteria. Experiments have been carried out using an image database of 30 grey level textures, all of them with 512×512 pixels in size, obtaining correct classification rates between 95% and 100%, according to the classification criterion used.     

High performance implementation of texture features extraction algorithms using FPGA architecture

The most popular second-order statistical texture features are derived from the co-occurrence matrix, which has been proposed by Haralick. However, the computation of both matrix and extracting texture features are very time consuming. In order to improve the performance of co-occurrence matrices and texture feature extraction algorithms, we propose an architecture on FPGA platform. In the proposed architecture, first, the co-occurrence matrix is computed then all thirteen texture features are calculated in parallel using computed co-occurrence matrix. We have implemented the proposed architecture on Virtex 5 fx130T-3 FPGA device. Our experimental results show that a speedup of 421[× yields over a software implementation on Intel Core i7 2.0 GHz processor. In order to improve much more performance on textures, we have reduced the computation of 13 texture features to 3 texture features using ranking of Haralick’s features. The performance improvement is 484×.     

FPGA-based fast computation of gray-level morphological granulometries

Morphological granulometries constitute one of the most useful and versatile image analysis techniques applied to a wide range of tasks, from size distribution of objects, to feature extraction and to texture characterization in industrial and research applications where high-performance instrumentation and online signal processing are required. Since granulometries are based on sequences of openings with structuring elements (SEs) of increasing size, they are computational demanding on non-specialized hardware. In this paper, a pipelined hardware architecture for fast computation of gray-level morphological granulometries is presented, centered around two systolic-like processing arrays able to process with flat SEs of different shapes and sizes. To validate the proposed scheme, the architecture was modeled, simulated and implemented into a field programmable gate array. Implementation results show that the architecture is able to compute particle size distribution on 512 × 512 sized images with flat non-rectangular SEs of up to 51 × 51, in around 60 ms at a clock frequency of 260 MHz. It is shown that a speed up over two orders of magnitude is obtained compared to a naive software implementation. The architecture performance compares favorably to similar hardware architectural schemes and to optimized high-performance graphical processing units-based implementations.     

Automatic defect detection of texture surface with an efficient texture removal network

Automated defect inspection of texture surface is still a challenging task in the industrial automation field due to the tremendous changes in the appearance of various surface textures. We present a simple but powerful image transformation network to remove textures and highlight defects at full resolution. The simple full convolution network consists only of 3 × 3 regular convolution and several dilated convolution blocks, which makes it compact and able to capture multi-scale features effectively. To further improve the ability of the network to suppress texture and highlight defects, a polynomial loss function combining perceptual loss, structural similarity loss and image gradient loss is proposed. In addition, a semi-automatic annotation method mainly composed of wavelet transform and relative total variation is designed to generate a data set of image pairs containing the original texture image and the desired texture removal image. We conducted experiments on a milled metal surface defect dataset and an open data set containing various textured backgrounds to evaluate the performance of our method. Compared with other convolutional neural network approaches, the results demonstrate the superiority of the proposed method. The method has been applied to the surface defect online detection system of an aluminum ingot milling production line, which effectively improves the surface inspection efficiency and product quality.     

联合深度学习和宽度学习的纹理样图自动提取

目的 纹理样图是指一幅用于描述纹理特征的图像,纹理样图多样性在纹理合成任务中是至关重要的,它可以为合成的纹理带来更丰富、多样和逼真的外观,同时为艺术家和设计师提供了更多的创作灵感和自由度。当前,纹理样图的提取主要通过手工剪裁和算法自动提取,从大量的图像中手工剪裁提取出高质量的纹理样图十分耗费精力和时间,并且该方式易受主观驱动且多样性受限。目前先进的纹理样图自动提取算法基于卷积神经网络的Trimmed T-CNN(texture convolutional neural network)模型存在推理速度慢的问题。基于此,本文致力于利用互联网上丰富的图像资源,自动快速地从各种图像中裁剪出理想且多样的纹理样图,让用户有更多的选择。方法 本文提出一个结合深度学习和宽度学习的从原始图像中自动提取纹理样图的方法。为了获取理想的纹理样图,首先通过残差特征金字塔网络提取特征图,有效地从输入图像中识别样图候选者,然后采用区域候选网络快速自动地获取大量的纹理样图候选区域。接下来,利用宽度学习系统对纹理样图的候选区域进行分类。最后,使用评分准则对宽度学习系统的分类结果进行评分,从而筛选出理想的纹理样图。结果...     

Robust Boosted Parameter Based Combined Classifier for Rotation Invariant Texture Classification

Texture analysis and classification remain as one of the biggest challenges for the field of computer vision and pattern recognition. This article presents a robust hybrid combination technique to build a combined classifier that is able to tackle the problem of classification of rotation-invariant 2D textures. Diversity in the components of the combined classifier is enforced through variation of the parameters related to both architecture design and training stages of a neural network classifier. The boosting algorithm is used to make perturbation of the training set using Multi-Layer Perceptron (MLP) as the base classifier. The final decision of the proposed combined classifier is based on the majority voting. Experiments’ results on a standard benchmark database of rotated textures show that the proposed hybrid combination method is very robust, and it presents an excellent texture discrimination for all considered classes, overcoming traditional texture modification methods.     

Texture Classification and Segmentation by Cellular Neural Networks Using Genetic Learning

We present a new single-chip texture classifier based on the cellular neural network (CNN) architecture. Exploiting the dynamics of a locally interconnected 2D cell array of CNNs we have developed a theoretically new method for texture classification and segmentation. This technique differs from other convolution-based feature extraction methods since we utilize feedback convolution, and we use a genetic learning algorithm to determine the optimal kernel matrices of the network. The CNN operators we have found for texture recognition may combine different early vision effects. We show how the kernel matrices can be derived from the state equations of the network for convolution/deconvolution and nonlinear effects. The whole process includes histogram equalization of the textured images, filtering with the trained kernel matrices, and decision-making based on average gray-scale or texture energy of the filtered images. We present experimental results using digital CNN simulation with sensitivity analysis for noise, rotation, and scale. We also report a tested application performed on a programmable 22 × 20 CNN chip with optical inputs and an execution time of a few microseconds. We have found that this CNN chip with a simple 3 × 3 CNN kernel can reliably classify four textures. Using more templates for decision-making, we believe that more textures can be separated and adequate texture segmentation (< 1% error) can be achieved.     

Supervised texture classification using a probabilistic neuralnetwork and constraint satisfaction model

The texture classification problem is projected as a constraint satisfaction problem. The focus is on the use of a probabilistic neural network (PNN) for representing the distribution of feature vectors of each texture class in order to generate a feature-label interaction constraint. This distribution of features for each class is assumed as a Gaussian mixture model. The feature-label interactions and a set of label-label interactions are represented on a constraint satisfaction neural network. A stochastic relaxation strategy is used to obtain an optimal classification of textures in an image. The advantage of this approach is that all classes in an image are determined simultaneously, similar to human perception of textures in an image.     

An economical tonal display for interactive graphics and image analysis data

The use of tonal displays in image analysis and interactive graphics has always dictated the use of expensive refresh memories for the display output device. This has involved the use of high speed digital drums, multiple head discs, and analog storage tubes. Recently, the introduction of very long shift registers has allowed the designer to consider their use for refresh memories. A prototype display using 1024 bit MOS static shift registers has been developed. It has been shown that a reasonable cost versus performance tradeoff can be obtained. The first efforts has resulted in a 128 × 128 × 4 bit (64k) memory; it is now in the process of being expanded to 256 × 256 × 8 bits (512k). This memory is cost competitive with digital disc memories and both cost and performance competitive with storage tube scan converters.     

Reconfigurable hardware for neural networks: binary versus stochastic

This paper is focused on hardware implementation of neural networks. We propose a reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. For this purpose, we use field-programmable gate arrays i.e. FPGAs. As the state-of-the-art FPGAs still lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement efficiently the computation performed by a neuron. This paper describes and compares the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time × area classic factor.     

Non‐Local Image Reconstruction for Efficient Computation of Synthetic Bidirectional Texture Functions

Visual prototyping of materials is relevant for many computer graphics applications. A large amount of modelling flexibility can be obtained by directly rendering micro‐geometry. While this is possible in principle, it is usually computationally expensive. Recently, bidirectional texture functions (BTFs) have become popular for efficient photorealistic rendering of surfaces. We propose an efficient system for the computation of synthetic BTFs using Monte Carlo path tracing of micro‐geometry. We observe that BTFs usually consist of many similar apparent bidirectional reflectance distribution functions. By exploiting structural similarity we can reduce rendering times by one order of magnitude. This is done in a process we call non‐local image reconstruction, which has been inspired by non‐local means filtering. Our results indicate that synthesizing BTFs is highly practical and may currently only take a few minutes for BTFs with 70 × 70 viewing and lighting directions and 128 × 128 pixels.     

An ASIC implementation of Kohonen's map based colour image compression

This paper presents a new hardware design for a neural network based colour image compression. The compressed image consists of a colour palette containing few best colours and the coded image. Kohonen's map neural network is applied to construct the colour palette and the coded image, both forming the compressed image. The Kohonen's map based compression results in linear time complexity (in the size of the image). It is advantageous over traditional JPEG in colour quantization applications and compression of images with limited colours. The architecture of the hardware unit is based on single instruction multiple data methodology. The architecture has been implemented in an application specific integrated circuit and results show that the proposed design achieves high speed allowing inputs at a video rate for compression of images up to size of 512×512 with low area requirement.     

Rotation and gray-scale-invariant texture analysis using radon and differential radon transforms based hidden Markov models

This study carries out rotation and gray-scale-invariant texture analysis of the textures in Brodatz album. A radon and differential radon transform based technique has been proposed to extract the features of the different textures at different orientations. These features have been used to train one-dimensional hidden Markov models - one for each texture. Testing and classification was done using percentage of correct classification (PCC) as figure of merit. The best percentage achieved was 99.9%.     

基于基元分布的误差可调纹理分类算法

提出一种基于纹理基元分布统计的纹理分类算法，选定一组代表像素变化的基元序列，计算每一个基元在纹理图像中的覆盖比例，用得到的纹理基元属性分布作为描述参数；由于相似纹理其属性也是相似的，同类纹理必然有接近的基元分布参数，计算参与实验的纹理样本的基元分布的互方差及互相关，与代表相似程度的阈值比较判断，由获得的共性来锁定同类纹理；为使同类纹理具有可参照的标准，产生针对每一类纹理的标准类分布。对Brodatz的111纹理不同相似程度的分类结果表明，该方法保证了统计结果与视觉判断的一致性，可用于纹理的分类及识别。     

Persistence of turbulent flow in microchannels at very low Reynolds numbers

A fully resolved numerical simulation of a turbulent microchannel flow, with uniformly spaced two-dimensional obstruction elements mounted at the wall and normal to the flow direction, was carried out at a very low Reynolds number of Re ≃ 970 based on the centerline velocity and the microchannel height. Employing the lattice Boltzmann numerical technique, all energetic scales of turbulence were resolved with about 19 × 10⁶ grid points (1261 × 129 × 128 in the x ₁, x ₂, and x ₃ directions). The simulated results confirm the self-maintenance of turbulence at such a low Reynolds number. Turbulence persisted over more than 1,000 turnover times, which was sufficiently long to prove its self-maintenance. These findings support the conjecture that turbulence developing in microchannels having rough walls can not only be initiated but also maintained at very low Reynolds numbers.