3-D MCM封装技术及其应用

介绍了超大规模集成电路（VLSI）用的3-D MCM封装技术的最新发展，重点介绍了3-D MCM封装垂直互连工艺，分析了3-D MCM封装技术的硅效率、复杂程度、热处理、互连密度、系统功率与速度等问题，并对3-D MCM封装的应用作了简要说明。     

3-DMCM实用化的进展

介绍了 3- D MCM的四种封装模式的应用实例 ,详细讨论了各种模式的工艺 ,优点及存在的问题。 3-D MCM是未来微电子封装的发展趋势。     

三维（3—D）封装技术

3-D多芯片组件（MCM）是未来微电子封装的发展趋势。本文介绍了超大规模集成（VLSI）用的3-D封装技术的最新进展,详细报导了垂直互连技术,概括讨论了选择3-D叠层技术的一些关键问题,并对3-D封装和2-D封装及分立器件进行了对比。     

三维MCM-C／A组件技术研究

本文研究了采用LTCC多层布线与铝阳极氧化多层布线工艺相结合的方法制作出三维高密度MCM组件（3D—MCM—C／A）。阐述了3D—MCM—C／A组件的结构,研究分析了LTCC基板与铝阳极氧化工艺之间的兼容性问题。通过LTCC工艺和LTCC基板抛光清洗工艺的控制以及过渡Ta层的设计解决了两者之间的兼容问题;采用LTCC隔板的方式实现组件的垂直互连。在LTCC基板表面采用薄膜淀积的方法以及特殊的“双刻蚀法”制作焊接区,满足了表面器件及垂直互连的焊接,实现了四层2D—MCM—C／A垂直互连。。     

LTCC 3D-MCM垂直互连技术研究

LTCC3D—MCM是采用低温共烧陶瓷（LTCC）为基板,实现有源元件和无源元件高密度集成的组件。垂直互连是完成2D-MCM转化为3D-MCM的重要途径。本文介绍了叠层型LTCC3D—MCM制作的基本工艺和几种垂直互连技术;对垂直互连所形成的焊料凸点、基扳之间的连接进行了分析和讨论。     

集成电路与零部件

美国Altera Corp和EPF 8050MPLD兼有高密度可编程逻辑、现场可编程互连芯片和MCM封装。这种装置是一个有5块芯片的MCM,它包括     

一种低成本的硅垂直互连技术

1引言 近年来，随着三维叠层封装技术和MEMS封装技术的发展，硅垂直互连技术正在受到越来越多的重视【1】。这一技术通过在硅片上制作出垂直电互连来实现芯片正面与背面或上下芯片之间的互连，从而缩短了互连线的长度并为芯片提供更为优异的电性能。其应用包括：台面MOS功率器件的倒装芯片封装【2】、垂直集成传感器阵列的制造【3】、RF-MEMS器件的封装【4】、高性能硅基板的开发【5】和芯片的三维叠层封装【6】。     

MCM的工艺技术发展

一、引言多芯片模块MCM：（MultichipModule）的基本概念是：把多块裸露的IC芯片组装在同一块多层高密度互连基板上，并封装在同一管壳中，形成一个多芯片功能组件。MCM是一种先进的电子组装技术，与过去的混合IC概念的关键区别在于“多块”“裸露”芯片直接组装在多层高密度互连基板上，若把一些单片器件组装在PC板上，则不能叫做MCM。采用MCM技术，其芯片之间的节距可缩得极小，层与层间以通孔金属化导线互连，因此，其多层互连线比常规PC板或混合IC要缩短一个数量级，由此导致一系列引人注目的重大优点。国际上的研究开发结果…     

多芯片组件将铸就世界辉煌

自80年代中期以来,国际上有关多芯片组件(MCM)的报道日益增多。人们从整机、制造和应用的不同角度,对MCM的定义不尽相同,对MCM的技术内涵也有不同的认识和理解。综合分析近年来国内外专家对MCM较普遍的看法,对MCM作如下定义比较妥当:MCM是将2个以上的大规模集成电路裸芯片和其它微型元器件互连组装在同一块高密度、高层基板上,并封装在同一管壳内构成功能齐全、质量可靠的电子组件。MCM是实现电子装备小型化、轻量化、高速度、高可靠、低成本电路集成不可缺少的关键技术,它与传统的混合IC主要区别在于MCM是采用“多块裸芯片”与“多层布线基板”,并实现“高密度互连”。     

光电多芯片组件的自由空间光互连技术研究

自由空间光互连 (FSOI)技术使用激光在自由空间中传播 ,其表现出的特性如速度和功耗等方面较之电在连线中的传输具有的明显优点 ,从而在具有巨大发展潜力的光电多芯片组件(OE- MCM)中得到了广泛的重视。本文在建立了 OE- MCM的物理模型、逻辑模型及开销模型的基础上 ,着重对 OE- MCM中的互连分割、互连距离 (MID)最小化和 FSOI互连设计几个方面进行了研究。     

A Test Methodology for High Performance MCMs

Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, andreliability benefits of MCMs. These advantages are only realized,however, if accompanied by an efficient test strategy whichverifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs thathave been mounted onto a multi-chip silicon substrate. A teststrategy, which addresses testing from the wafer level through tothe populated substrate, is detailed. This strategy uses acombination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high testquality at a reasonable cost. The methodology is then contrastedto alternative approaches.     

Embedded microstrip interconnection lines for gigahertz digitalcircuits

Transmission line structures are needed for the high-performance interconnection lines of GHz integrated circuits (ICs) and multichip modules (MCMs), to minimize undesired electromagnetic wave phenomena and, therefore, to maximize the transmission bandwidth of the interconnection lines. In addition, correct and simple models of the interconnection lines are required for the efficient design and analysis of the circuits containing the interconnection lines. In this paper, we present electrical comparisons of three transmission line structures: conventional metal-insulator-semiconductor (MIS) and the embedded microstrip structures-embedded microstrip (EM) and inverted embedded microstrip (IEM). In addition, we propose closed-form expressions for the embedded microstrip structures EM and IEM and validate the expressions by comparing with empirical results based on S-parameter measurements and subsequent microwave network analysis. Test devices were fabricated using a 1-poly and 3-metal 0.6 μm Si process. The test devices contained the conventional MIS and the two embedded microstrip structures of different sizes. The embedded microstrip structures were shown to carry GHz digital signals with less loss and less dispersion than the conventional MIS line structures. S-parameter measurements of the test devices showed that the embedded microstrip structures could support the quasi-TEM mode propagation at frequencies above 2 GHz. On the other hand, the conventional MIS structure showed slow-wave mode propagation up to 20 GHz. More than 3-dB/mm difference of signal attenuation was observed between the embedded microstrip structures and the conventional MIS structure at 20 GHz. Finally, analytical RLCG transmission line models were developed and shown to agree well with the empirical models deduced from S-parameter measurements     

不断推进的圆片级三维封装

当减小芯片面积时,3-D封装能减轻互相连接所带来的延迟问题,根据集成电路是否已经进行了3-D互相的设计,描述了3种选择方法。     

光电子多芯片组件中光互连能量分析

分析了光电子多芯片组件内自由空间光互连的单位比特能量需求 ,并与片间电互连情况进行了对比 ,最后给出了多芯片组件内光 -电互连能量平均转效的互连线长( break- even 1 ine)。     

Driver IC and COG Package Design

This paper investigates the interconnection between the driver integrated circuit (IC) and glass substrate via anisotropic conductive adhesive (ACF) of chip on glass package. The conductive particle deformation is evaluated using a novel method, optical microscope (OM) inspection. The proposed method is more convenient than the traditional approach using scanning electron microscopy applied in the manufacturing process. Interconnection performance is easily judged using OM, allowing poor interconnection between the driver IC and glass substrate to be screened out. Several types of driver ICs with different bump area ratios (total input bump area/total output bump area, input/output ratio) and length/width (L/W) ratios are designed in this experiment. The conductive particle deformations are investigated in this study. Driver ICs with L/W ratios larger than 15 have better conductive particle deformation uniformity at each position. The average deformation degree at the driver IC center position is larger than that at the side and edge positions. The deformation degree at the input position with a smaller bump area is better than that at the output position. The conductive resistance increases with the reliability testing time because of the thermal stress effect and softening of the ACF polymer material. The deformation degree is related to the conductive resistance of the interconnection. The conductive resistance is lower at the center and input positions with larger deformation degree.     

自组织神经网络在时延驱动的MCM系统划分中的应用

ＭＣＭ是 的一种新技术,划分是ＭＣＭ设计中极其重要的一个环节,本文应用Ｋｏｈｏｎｅｎ自组织神经网络求解以面积和时延为约束的,以芯片之间的边线代价和系统时钟周期为优化目标ＭＣＭ系统 发问题,算法用单元之间的联接度和组合逻辑单元的内部时延表示直接相联单元间的相似性,并应用模糊相似性变换建立间接相联单元间的相似性,算法将各单元映射到二维平面上,对应一个或者多个神经元,学习过程是通过单元之间有协作的移动,     

High-speed optical transmission systems using advanced monolithicIC technologies

The authors discuss the design and performance of monolithic ICs for multigigabit lightwave transmission systems including direct detection and coherent detection. The required function and performance of a lightwave transmitter and receiver are discussed. The fabricated ICs and their application to the transmission system are shown in a direct system. Microwave monolithic ICs for lightwave heterodyne detection and an interconnection technique are introduced. Future trends of ICs are discussed     

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.