Evidence for two distinct positive trapped charge components in NBTI stressed p-MOSFETs employing ultrathin CVD silicon nitride gate dielectric

Besides the generation of interface states and the associated positive trapped charge (N/sub tc1/), experimental results unambiguously show the generation of another positive trapped charge component (N/sub tc2/) during negative-bias temperature instability (NBTI) stressing of p-MOSFETs employing ultrathin silicon nitride gate dielectric. For a given gate stress voltage, N/sub tc2/ is generated at a much faster rate compared to N/sub tc1/. Under the pulsed gate condition studied, N/sub tc1/ could almost be completely annihilated, regardless of the NBTI stress voltage, whereas only partial annihilation of N/sub tc2/ is observed. This more resistant nature of N/sub tc2/ to post-stress relaxation has serious implications on the dynamic NBTI reliability of these p-MOSFETs.     

Recovery of negative bias temperature instability induced degradation of p-MOSFETs with SiON gate dielectric

This paper investigates the recovery property of p-MOSFETs with an ultra-thin SiON gate dielectric which are degraded by negative bias temperature instability (NBTI). The experimental results indicate that the recovery of the NBTI degradation occurs through an electrical neutralization of the NBTI-induced positive charges at the SiON/Si interface and in the gate dielectric. The neutralization of interface charges was a fast process occurring just after the device returned to the recovery state. The neutralization of positive charges in the gate dielectric was a slow process associated with the electron injection into the gate dielectric. Below the gate voltage for strong accumulation, the amount of recovery increased with an increase of the gate voltage. A further increase of gate voltage did not affect the amount of recovery. These experimental results indicate that the major cause of the recovery is a neutralization of the NBTI-induced positive charges by electrons instead of a hydrogen passivation of the NBTI-induced defect sites.     

A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs

A comprehensive modeling framework involving mutually uncorrelated contribution from interface trap generation and hole trapping in pre-existing, process related gate insulator traps is used to study NBTI degradation in SiON and HKMG p-MOSFETs. The model can predict time evolution of degradation during DC and AC stress, time evolution of recovery after stress, impact of stress and recovery bias and temperature, and impact of several AC stress parameters such as pulse frequency, duty cycle, duration of last pulse cycle (half or full) and pulse low bias. The model can successfully explain experimental data measured using fast and ultra-fast methods in SiON and HKMG devices having different gate insulator processes. The trap generation and trapping sub components of the composite model have been verified by independent experiments. Data published by different groups are reconciled and explained. The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices.     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

Negative bias temperature (NBT) instability of p-MOSFETs with ultrathin SiON gate dielectric has been investigated under various gate bias configurations. The NBT-induced interface trap density (/spl Delta/N/sub it/) under unipolar bias is essentially lower than that under static bias, and is almost independent of the stress frequency up to 10 MHz. On the contrary, /spl Delta/N/sub it/ under bipolar pulsed bias of frequency larger than about 10 kHz is significantly enhanced and exhibits a strong frequency dependence, which has faster generation rate and smaller activation energy as compared to other stress configurations. The degradation enhancement is attributed to the energy to be contributed by the recombination of trapped electrons and free holes upon the silicon surface potential reversal from accumulation to inversion.     

Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

Recent advances in experimental techniques (on-the- fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale. Such measurements over wider temperature range (-25degC to 145degC), film thicknesses (1.2-2.2 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation. In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes.     

Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling

For the first time, a dynamic negative bias temperature instability (DNBTI) effect in p-MOSFETs with ultrathin gate oxide (1.3 nm) has been studied. The interface traps generated under NBTI stressing corresponding to p-MOSFET operating condition of the "high" output state in a CMOS inverter, are subsequently passivated when the gate to drain voltage switches to positive corresponding to the p-MOSFET operating condition of the "low" output state in the CMOS inverter. Consequently, this DNBTI effect significantly prolongs the lifetime of p-MOSFETs operating in a digital circuit, and the conventional static NBTI (SNBTI) measurement underestimates the p-MOSFET lifetime. A physical model is presented to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.     

The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly $I_{rm DLIN}$ Technique

Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly I_DLIN technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface.     

Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si

We have successfully demonstrated high-performance p-MOSFETs in germanium grown directly on Si using a novel heteroepitaxial growth technique, which uses multisteps of hydrogen annealing and growth to confine misfit dislocations near the Ge-Si interface, thus not threading to the surface as expected in this 4.2% lattice-mismatched system. We used a low thermal budget process with silicon dioxide on germanium oxynitride (GeO/sub x/N/sub y/) gate dielectric and Si/sub 0.75/Ge/sub 0.25/ gate electrode. Characterization of the device using cross-sectional transmission electron microscopy and atomic force microscopy at different stages of the fabrication illustrates device-quality interfaces that yielded hole effective mobility as high as 250 cm/sup 2//Vs.     

Hot-carrier stress effects on gate-induced-drain leakage current in n-channel MOSFETs studied by hydrogen/deuterium isotope effect

The degradation of gate-induced-drain leakage (GIDL) current under hot-carrier stress (HCS) has been studied in n-channel MOSFETs that were annealed in hydrogen (H) or deuterium (D). It is found that the degradation of GIDL current (I/sub GIDL/) can be effectively suppressed by deuterium passivation of interface traps. By using the H/D isotope effect, the impacts of oxide charge trapping (/spl Delta/N/sub ox/) and interface trap generation (/spl Delta/N/sub it/) on I/sub GIDL/ are successfully separated. The results indicate that, depending on stress and measurement conditions, I/sub GIDL/ may increase or decrease under HCS. /spl Delta/N/sub ox/ alters I/sub GIDL/ at high electric fields by varying the band-to-band tunneling current. /spl Delta/N/sub it/ alters I/sub GIDL/ at a low electric field by introducing a trap-assisted leakage component. Furthermore, evidence of hole trapping at the peak substrate current stress is indisputably presented for the first time and its impact on I/sub GIDL/ is discussed.     

On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

A common framework for interface-trap (N/sub IT/) generation involving broken /spl equiv/Si-H and /spl equiv/Si-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress. Holes (from inversion layer for pMOSFET NBTI, from channel due to impact ionization, and from gate poly due to anode-hole injection or valence-band hole tunneling for nMOSFET HCI) break /spl equiv/Si-H bonds, whose time evolution is governed by either one-dimensional (NBTI or FN) or two-dimensional (HCI) reaction-diffusion models. Hot holes break /spl equiv/Si-O bonds during both FN and HCI stress. Power-law time exponent of N/sub IT/ during stress and recovery of N/sub IT/ after stress are governed by relative contribution of broken /spl equiv/Si-H and /spl equiv/Si-O bonds (determined by cold- and hot-hole densities) and have important implications for lifetime prediction under NBTI, FN, and HCI stress conditions.     

Analytical Low Frequency NBTI Compact Modeling with H<Subscript>2</Subscript> Locking and Electron Fast Capture and Emission

Besides reaction-diffusion theory explaining the generation and passivation of interface trap (ΔN_IT), hole trapping/de-trapping in preexisting gate insulator traps and transient charge occupancy in ΔN_IT are also combined to describe the characteristic of NBTI degradation. However, it is found that H₂ locking effect and Electron Fast Capture/Emission play key roles in the NBTI degradation. In this paper, an analytical low frequency AC NBTI compact model has been proposed to accurately predict the shift in threshold voltage. Two fitting parameters (α and F_FAST) have been introduced to account for the H₂ locking and fast electron capture and emission. The comparison between the proposed model and the experimental data has been carried out, and the results show that our proposed can catch the kinetics of NBTI degradation under low frequency AC stress conditions.     

The role of electron traps on the post-stress interface trapgeneration in hot-carrier stressed p-MOSFETs

The generation of interface traps in p-MOSFETs subjected to hot-electron injection is found to proceed even after the stress has been terminated. The extent of post-stress interface trap generation is strongly dependent on the magnitude of the preceding hot-electron stress, as well as the magnitude and polarity of the gate voltage during relaxation. Trap generation is enhanced for negative gate voltage anneal, but suppressed for positive gate voltage anneal. For a given stress-induced damage, the corresponding trap generation kinetics can be completely described by a single characteristic, which is shifted in time according to the magnitude of the applied gate voltage. Existing interface trap generation models are discussed in the light of the experimental results. A new model involving the tunneling of holes from the inversion layer to deep-level electron traps is proposed. Similar post-stress effect observed for hot-electron stressed n-MOSFETs provides additional support for the model. Our work suggests that near-interface electron traps, apart from the well-known hole traps, may also significantly affect the long-term stability of the Si-SiO₂ interface     

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.     

Process dependence of BTI reliability in advanced HK MG stacks

Bias temperature instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.     

Hole energy dependent interface trap generation in MOSFET Si/SiO/sub 2/ interface

The nature and composition of generated interface-trap (/spl Delta/N/sub IT/) in p-MOSFETs is studied as a function of hole energy. By observing the time dependence of generation during stress and the amount of recovery after stress, it is shown that /spl Delta/N/sub IT/ is due to both broken /spl equiv/Si--H and /spl equiv/Si--O-- bonds, their ratio governed by hole energy. In the absence of hot holes /spl Delta/N/sub IT/ is primarily composed of broken /spl equiv/Si--H, which show a lower power-law time exponent and a fraction of which anneal after stress. Additional /spl Delta/N/sub IT/ is created in the presence of hot holes, which is due to broken /spl equiv/Si--O-- bonds. These traps show a much larger power-law time exponent, and they do not anneal after stress. These observations have important implications for lifetime prediction under negative bias temperature instability, Fowler-Nordheim, and hot carrier injection stress conditions.     

Hole traps in silicon dioxides. Part I. Properties

As the downscaling of gate oxides continues, trap density in the oxide bulk will reduce, but positive charges formed near to the SiO/sub 2//Si interface become relatively important. For gate oxides used in industry, hole trapping is the most important process for positive charge formation. Apart from as-grown hole traps, we recently reported that new hole traps were generated by electrical stresses. Information on these hole traps, however, is still limited. In part I of this work, properties of both generated and as-grown hole traps are investigated. For the first time, it will be clearly shown that generated hole traps consist of two components; cyclic positive charges (CPC) and antineutralization positive charges (ANPC). The charging and discharging rates of CPC are similar, while the neutralization of ANPC is much more difficult than its charging. Differences between them are also observed in generation kinetics and dependence on measurement temperature. Efforts will be made to explain their differences in terms of energy levels and to link them with positive charges reported in earlier works. We will also show that as-grown traps, regardless their distance from the interface, are not responsible for either ANPC or CPC. This is to say that generated hole traps are not the same as as-grown traps and their differences will be highlighted. In part II, hole trap generation mechanisms will be investigated.     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Time-dependent degradation due to negative bias temperature instability of p-MOSFET with an ultra-thin SiON gate dielectric

This paper presents the time-dependence of the negative bias temperature instability (NBTI) degradation of p-MOSFETs with an ultra-thin silicon oxynitride gate dielectric. The concentrations of nitrogen in the gate dielectric were approximately 3% and 10%. The device with 10% nitrogen concentration had unique time-dependent degradation characteristics due to the nitrogen enhanced NBTI effect. It degraded significantly just after application of an NBTI stress. After this initial degradation, a fast and slow degradation followed in sequence. The initial, fast, and slow degradations appear to be associated with the deep donor effect of nitrogen, the diffusion of ionic and neutral hydrogen combined with Si-H bond breaking, and the diffusion of neutral hydrogen combined with O-H bond breaking, respectively. Owing to the slow down of the NBTI degradation after the initial and fast degradations, the lifetime for the device with 10% nitrogen concentration was three times longer than that with 3% nitrogen concentration.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.