Pipelined GaAs carry lookahead adder

Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 μm E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to reduce the power budget are essential. As a result. The design of a four bit pipelined GaAs CLA operating at 800 MHz and exhibiting less than 1.8 mW of power dissipation is presented     

A 32-bit carry lookahead adder using dual-path all-N logic

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.     

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder     

Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications     

DPTL 4-b carry lookahead adder

Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1-μm non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890×0.652 mm² (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers)     

A novel multiplexer-based low-power full adder

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.     

A low-power 22-bit incremental ADC

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 /spl mu/V/sub RMS/), the DC offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 /spl mu/A current during conversion.     

一种新的加法器进位旁路电路

,从逻辑关系上优化了进位旁路加法器中的进位旁路电路,并采用差分串联电压开关传输门(DCVSPG)逻辑电路实现.该方法解决了传统静态曼彻斯特链进位旁路电路的逻辑冲突问题,又避免了动态曼彻斯特链进位旁路电路在预充阶段的延迟和功耗开销.DCVSPG逻辑进位旁路比静态曼彻斯特链进位旁路和动态曼彻斯特链进位旁路分别节省了25%和...     

A high-speed energy-efficient 64-bit reconfigurable binary adder

Datapaths for media signal processing are typically built using programmable computational elements such as adders and multipliers, which can be run-time reconfigured to operate on simple integers with 8, 16, or 32 bits of precision. In this brief, a new high-speed energy-efficient reconfigurable adder for media signal processing is presented. The proposed circuit is based on carry-propagation schemes and can be partitioned to perform one 64-, two 32-, four 16-, and eight 8-bit additions. When the Austria Mikro System (AMS) 0.35 /spl mu/m 2-poly 3-metal 3.3 V CMOS (CSD) process is used to produce layout, a worst propagation delay of about 4.9 ns and an average energy dissipation of about 181 /spl mu/W/MHz are obtained.     

High-speed operation of a low-power 4-bit serial-to-parallel converter

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit yield for use as a core element in an address decoder or a demultiplexer. First, the circuit design and optimization are discussed. Simulated performance of the circuit shows proper operation at 20 Gb/s, with a discussion of its potential for use at even higher rates. The power dissipation is computed to be 28 /spl mu/W in continuous operation and the predicted within-wafer yield is 95%. Measured results are then given for data rates of 100 Mb/s and 1 Gb/s.     

一种低功耗16-bit双向进位加法器设计

在地址产生单元中,循环寻址和位反序寻址需要进行大量的正向加法和逆向加法操作,加法器功耗常常在整个地址产生单元占很大比重.提出了一种基于180nm的低功耗16-bit双向进位加法器,采用传输门与互补CMOS混合结构,可进行正向和逆向加法.并在不同的电容负载情况下通过HSPICE在1.8V供电电压下对所提出加法器进行仿真,得到的功耗与功耗延时积(PDP)与传统的28T加法器相比,具有较大改进.     

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-V/sub T/ semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.     

A low-power adder operating on effective dynamic data ranges

To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2's complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2's complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.     

Self-timed Manchester chain carry propagate adder

The authors present a self-timed adder that uses two Manchester chains to propagate carries in a two-rail code. With the inclusion of buffers in the chains, the adder met the timing conditions typical of an asynchronous design based on the `bundled-data, bounded-delay' model and is significantly faster than self-timed adders with restoring logic and similar complexity     

64-bit carry-select adder with reduced area

A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder     

一种低功耗10位流水线结构的CMOS A/D转换器的设计

本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2.     

2-bit adder: carry and sum logic circuits at 19 GHz clock frequencyin InAlAs/InGaAs HBT technology

Carry and sum circuits for a 2-bit adder used in a pipelined 2N-bit adder-accumulator architecture are reported. To obtain high clock rates in a design with multiple gate delays a novel merged AND-OR-Latch structure using four-level series gated current steering logic is employed. These integrated circuits were fabricated in InAlAs/InGaAs transferred substrate heterojunction bipolar transistor technology and operate up to 19 GHz clock rate     

超前进位加法器的一种优化设计

描述了超前进位加法器的一种优化设计.在结构上采用按4位分组进行超前进位的方法达到并行、高速的目的.为了在高速运算的同时降低功耗,对求和式子进行了逻辑变换;在晶体管级进行优化的单元电路设计,可减小延时、降低整个电路的面积和功耗.     

A new low-power GaAs two-single-port memory cell

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm² using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V     

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V _dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).