Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Increased junction breakdown voltages in silicon-on-insulatordiodes

A junction breakdown model and the results of PISCES II simulations are presented for silicon-on-insulator (SOI) devices. This model shows the dependence of breakdown voltage in fully depleted (FD) SOI diode on the backgate bias, the properties of the buried oxide layer, and the device parameters. Breakdown in a thin FD SOI diode is quite different from that observed in a thicker, partially depleted (PD) diode. The analysis is supported by breakdown voltage measurements of separation by implantation of oxygen (SIMOX)-based SOI diodes, the results of which suggest that body breakdown is dominant in FD SOI diodes, and the junction curvature effect is dominant in PD SOI diodes. Furthermore, the results also show that breakdown voltage in the FD SOI diode is higher than their bulk-silicon counterpart and can be further increased by applying the appropriate backgate bias     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Short-channel single-gate SOI MOSFET model

The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.     

Modes of operation and radiation sensitivity of ultrathin SOItransistors

Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology     

全耗尽SOI MOSFET及CMOS／SOI电路的研究

采用ＳＩＭＯＸ材料，研制了一种全耗尽ＣＭＯＳ／ＳＯＩ模拟开关电路，研究了全耗尽ＳＯＩ ＭＯＳ场效应晶体管的阈值电压与背栅偏置的依赖关系，对漏源击穿的Ｓｎａｐｂａｃｋ特性进行分析，介绍了薄层ＣＭＯＳ／ＳＩＭＯＸ制作工艺，给出了全耗尽ＣＭＯＳ／ＳＯＩ电路的测试结果。     

Subthreshold characteristics of fully depleted submicrometer SOIMOSFET's

In this paper, an analytic current-voltage model in the subthreshold regime for submicrometer fully depleted (FD) silicon-on-insulator (SOI) MOSFET's is presented. This model takes into account the dependence of the effective depleted charge on the drain bias and the voltage drop in the substrate region underneath the buried oxide. In addition to predicting accurate subthreshold current-voltage characteristics and subthreshold slope, this model can be used to predict important Short Channel Effects (SCE) such as the threshold voltage roll-off and Drain-Induced Barrier Lowering (DIBL). This model is verified by comparison to a two-dimensional device simulator, MEDICI. Good agreement is obtained for SOI channel lengths down to 0.25 μm     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs

The zero temperature coefficient (ZTC) is investigated experimentally in partially (PD) and fully depleted (FD) SOI MOSFET fabricated in a 0.13 μm SOI CMOS technology. A simple model to study the behavior of the gate voltage at ZTC (V_ZTC) is proposed in the linear and the saturation region. The influence of the temperature mobility degradation on V_ZTC is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices, which is responsible for the V_ZTC decrement observed in FD instead of the increment observed in PD devices when the temperature increases. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplification used for the V_ZTC model as a function of temperature in the linear and the saturation region.     

A dual body SOI structure for mixed analog-digital mode circuits

A new silicon-on-insulator (SOI) structure for mixed analog-digital applications is proposed where analog and digital MOSFET's are independently optimized. Two types of field oxide are introduced so that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted. From measurements of the body related device characteristics such as the output resistance, the variation of threshold voltage and transconductance, 1/f noise, body resistance, and the self-heating effect, it is shown that the proposed structure is promising for SOI technology in mixed analog-digital mode circuit applications     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型(英文)

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

体效应对超深亚微米SOI器件总剂量效应的影响

研究体偏置效应对超深亚微米绝缘体上硅（SOI,Silicon-on-insulator）器件总剂量效应的影响.在TG偏置下,辐照130nm PD（部分耗尽,partially depleted）SOI NMOSFET（N型金属-氧化物半导体场效应晶体管,n-type Metal-Oxide-Semiconductor Field-Effect Transistor）器件,监测辐照前后在不同体偏压下器件的电学参数.短沟道器件受到总剂量辐照影响更敏感,且宽长比越大,辐射导致的器件损伤亦更大.在辐射一定剂量后,部分耗尽器件将转变为全耗尽器件,并且可以观察到辐射诱导的耦合效应.对于10μm/0.35μm的器件,辐照后出现了明显的阈值电压漂移和大的泄漏电流.辐照前体偏压为负时的转移特性曲线相比于体电压为零时发生了正向漂移.当体电压Vb=-1.1V时部分耗尽器件变为全耗尽器件,|Vb|的继续增加无法导致耗尽区宽度的继续增加,说明体区负偏压已经无法实现耗尽区宽度的调制,因此器件的转移特性曲线也没有出现类似辐照前的正向漂移.     

Fault detection in CMOS/SOI mixed-signal circuits using the quiescent current test

Main stream bulk CMOS and the variants of silicon-on-insulator (SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2–3 times lower static power consumption in fully depleted CMOS/SOI compared to bulk CMOS allows quiescent current testing also for high performance analogue circuits at an acceptable defect resolutions. From first simulations and technological considerations, it turned out that quiescent current tests are able to detect not only commonly known defects, but also SOI specific defects such as self-heating, kink-effect or the parasitic bipolar behaviour. It is further shown that in partially depleted thick-film SOI, the kink-effect and parasitic bipolar transistor support the quiescent current test for some specific defects as they elevate the defective quiescent current level. In fully depleted kink-free SOI circuits, the kink-effect may occur due to process failures but then can be detected by quiescent current tests. A special fault simulation model for the kink-effect is presented. The I_ccq test technique is studied for a CMOS/SOI Miller operational amplifier. Normal 6-σ variation of the aspect ratio and the threshold voltage do not jeopardise the defect detection in the quiescent current. First, results confirm the good detection capabilities of the quiescent current test, in particular, of failures which are not visible in the output voltage.     

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.     

Generation-recombination noise in the near fully depleted SIMOX SOI n-MOSFET - physical characteristics and modeling

Noise measurement in the linear regime of the device characteristics shows the evolution of an important Lorentzian-like component in the thin-film SIMOX silicon-on-insulator (SOI) n-MOSFET, during the transition from fully depleted to near fully (or partially) depleted operation. The same noise component co-exists with another Lorentzian-like component commonly observed in the kink region, thus distinguishing it from the latter, which is associated with a shot-noise mechanism. Evidence unambiguously shows that local potential fluctuations, caused by random generation-recombination (G-R) processes at bulk defects in the depleted SOI film, are primarily responsible. Extracted trap energy of /spl sim/0.4-0.45 eV below the silicon conduction band edge confirms the involvement of deep-level electron traps, which are probably linked to the residual oxygen and SiO/sub 2/ precipitates in the SOI film. A new analytical G-R noise model yields bulk traps with an average density of /spl sim/10/sup 16/ cm/sup -3/, situated at /spl sim/22-32 nm from the front interface. With an area density comparable to that of the front interface states, the proximity of these bulk traps to the conducting channel in thin-film SIMOX SOI devices accounts for the dominance of bulk-trap induced G-R noise over conventional 1/f noise due to near-interface oxide traps.     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs