Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.     

Low-voltage CMOS adjustable current mirror

A novel scheme for an adjustable low-voltage CMOS current mirror is introduced. The proposed current mirror provides continuous gain adjustment, while it simultaneously features the attractive characteristic of low-voltage operation. The behaviour of the proposed topology has been experimentally verified through a first-order lowpass filter fabricated in AMS 0.35 μm CMOS technology.     

Tunable linear CMOS current mirror

Based on triode MOSFETs as tunable devices, a tunable linear current mirror is proposed, whose current gain is tunable over a wide range. Simulations show that, total harmonic distortion on the output current is within 2% for a tuning range of almost five octaves. Although the structure is in the form of an active-input current mirror, keeping the tuned MOSFETs in triode region significantly relaxes the stability problems of an active-input current mirror. This issue is revealed by theoretical analyses and further simulations are included for demonstration. An application example is also supplied.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

A very high performance compact CMOS current mirror

This paper proposes a very high performance current mirror (CM), where output current accurately copies the input current without carrying any offset component. Compact implementation of Garimella et al. CM structure has been combined with super cascode configuration to achieve the proposed very high performance CM. The proposed CM offers extremely high output resistance, very low input resistance and high degree of copying accuracy over a wide operating current range. Small signal analysis is carried out to validate the performance characteristics of the circuit. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology, using a single supply voltage of 1.5 V. The circuit is shown to have high current copying accuracy for a range of (0–500 µA) with an error less than 0.0016 % and has no offset current at the output side. The robustness of the proposed CM against the variations in device parameters and temperature changes has been reflected in simulations by carrying Monte Carlo and temperature analysis. The simulation results show that the proposed circuit provides very high output resistance of 55.76 GΩ and a very low input resistance of 0.07 Ω.     

Compact low voltage four quadrant CMOS current multiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

A regulated body-driven CMOS current mirror for low-voltage applications

A CMOS current mirror (CM) based on the body-driven technique and active feedback scheme is presented. The proposed CM is immune to the threshold voltage limitation and offers much higher accuracy over wider current operating range than other body-driven CMs. The complete analysis of the input-output characteristics, system dc current transfer error, frequency, and noise performance is provided. By using a 1.5V/1V single power supply and 0.18-/spl mu/m n-well process, SPECTRE simulation results validate the analytical results and the overall good performance in terms of wider input-output voltage swing, lower input resistance, and larger output resistance compared with the conventional high-swing cascode CM.     

A wide dynamic range continuously adjustable CMOS current mirror

A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

New high-compliance CMOS current mirror with low harmonic distortion for high-frequency circuits

A new low-distortion high-compliance CMOS current mirror is presented. The large-signal nonlinear characteristic of MOS transistors in saturation, combined with capacitances present in current mirror circuits, causes harmonic distortion. This effect is explained for a well-known current mirror circuit, and the new circuit is described which substantially reduces harmonic distortion while using only one extra standard process component.<>     

基于自偏置电流镜的CMOS红外焦平面读出电路

针对高精度红外焦平面阵列应用设计了一种具有高注入效率、大动态范围、稳定的探测器偏压、小面积和低功耗的自偏置电流镜注入CMOS读出电路.所设计的电路结构包括一种由自偏置的宽摆幅PMOS共源共栅电流镜和NMOS电流镜构成的反馈结构读出单元电路和相关双采样电路.对所设计电路采用Chartered 0.35 μm CMOS工艺进行了流片.测试结果显示:电路线性度达到了99%,探测器两端偏压小于1mV.电路输入阻抗近似为0,单元电路面积为10μm×15μm,功耗小于0.4μW.电量存储能力3108电子.测试结果表明:电路功能和性能都达到了设计要求.     

Synchronizable Compact CMOS Oscillator

This letter describes the design and implementation of a synchronizable compact CMOS oscillator. By using a fully differential topology, a reduction in area occupancy together with an improved robustness in front of on-chip interferences is achieved. Post-layout simulation results and experimental results for a standard CMOS 0.35 m technology are presented to validate the functionality of the tunable oscillator.     

Compact low-voltage CMOS four-quadrant analogue multiplier

A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the sub-currents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 mum CMOS process are provided     

A high-performance CMOS power amplifier

A high-performance CMOS power amplifier consisting of a new input stager especially suited to power amplifier applications and a variation on a class AB output stage is presented. The amplifier has been fabricated using a conventional silicon gate p-well process. The configuration results in several performance improvements over previously reported high-output current amplifiers without requiring process enhancements. Design details and experimental results are described.     

Min-net winner-take-all CMOS implementation

A charge-based winner-take-all (WTA) circuit is proposed. This WTA circuit is a min-net capable of selecting the minimum value among its input nodes and gives only one low voltage for the corresponding output node. The charge-based circuit uses a power supply of 3 V, with low power dissipation due to the lack of static DC current involved. The WTA circuit is used in associative neural networks.<>     

A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z?, good linearity and excellent output–input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.     

CMOS parametric current amplifier

The current amplifier presented is based on a gate-bulk-source translinear loop of MOSTs biased in weak inversion. Large gain factors are achieved with the consumption of only a small area. Gain is controlled by a ratio of bias currents     

High-precision CMOS current conveyor

A CMOS current conveyor suitable for high-precision analogue signal processing is presented. Local negative feedback is employed for minimising voltage variations at critical nodes, thus achieving very high accuracy in the transfer characteristics. Simulation results confirming the performance of the circuit are included