电子产品

自从二十世纪八十年代个人计算机和移动通信的飞速发展.促使电子示波器从模拟方式跃进到数字方式的转变.以适应数字基的信息时代对波形测量的要求。随着数字集成电路时钟频率的不断升高,集成度的不断翻番,现今时钟频率500～1000MHz已非常普遍,例如微处理器的时钟采用2GHz,移动通信的载频采用1.8GHz。为了实现从集成电路芯片至信息技术产品的开发、制造和维护,数字示波器需     

一种从E1信号中提取时钟的全数字锁相环设计与实现

我们提出一种从Ｅ１信号中提取时钟的全数字锁相环,并采用半脉冲移动技术设计数控振荡器,使得时钟占空比的误差小于４％,经实验证实,完全可以用于从数字信号中提取时钟,由于数字集成电路发展而采用数字锁相环对系统集成大有好处。     

数字钟电路的设计

数字钟是采用数字电路实现的计时装置,主要介绍了555定时器构成的多谐振荡电路作为时钟源的数字钟的基本组成和工作原理。电路元件大多为中小规模集成电路,是现下较为流行的数字钟的制作方案。     

基于延迟锁相环和锁频环结构的全数字同步倍频器

针对现有基于PLLs/DLLs的全数字化同步倍频器结构存在的不足,本文提出了基于一种双环结构的全数字同步倍频器。它由延迟锁相环和锁频环共享一个共同的参考时钟信号(FREF)构成,不需要任何模拟组件。它可以采用Verilog-HDL语言设计,可在Altera DE2-70开发板上实现合成,而且可以很容易地适应于不同的FPGA系列以及作为一个集成电路实现,同时也可用于为分布式数字处理系统以及片上系统的片内/片间通信提供时钟参考;实验结果表明,本文所提出的结构相比于现有的结构,能够获得更高频率的输出时钟信号,提供更好的频率分辨率、更好的抖动性能和高倍乘因子。     

同步数字集成电路设计中的时钟偏移分析

随着社会经济的迅速发展,同步集成电路的设计应用,在推动我国电子行业发展的同时,还给人们的日常生活带来了极大的便利。然而在实际设计中,受时钟偏移的影响,同步数字集成电路的整体性能无法得到保障,这些,都将成为当前同步数字集成电路设计人员急需完善的问题。在此,本文针对同步数字集成电路设计中的时钟偏移这一问题,做以下论述。     

数字电视发端调制器芯片时序优化设计与实现

设计数字集成电路时,关键是要满足时序的约束。时钟树综合是芯片设计后端优化时序过程中至关重要的一环,尤其是在复杂的超大规模高速集成电路设计中,它将直接影响最后的流片。其中时钟偏斜是影响时钟的重要因素。本文以SMIC 0.18μm工艺数字电视发端调制器芯片为例,前端提出新的获得同步分频时钟的方法,后端使用Synopsys的Astro工具来进行手动时钟树综合和时序优化,在满足时序设计要求的同时减小了芯片面积。     

高速数据链路时钟信号锁相环带宽的选择

时钟信号为所有集成电路和电子系统提供基准时序，消费电子应用中通常使用简单石英晶体产生参考时钟，但是其他应用有更复杂的时序要求，往往需要能提供同步、生成和分配功能的时钟产品。如在无线基础设施和医疗成像设备中，往往需要高保真模拟到数字的信号转换，下一代设计需要更高分辨率和更快的数据传输速率。     

看懂数字功放电路也简单

由于数字功放中的信号处理电路很容易做成集成电路．所以现在的数字功放都是以集成电路为中心来构成的。下面介绍几种常用的而且具有代表性的集成数字功放电路．这样．你不仅了解了数字功放．而且自己还可以DIY数字功放了。     

基于单片机的多功能时钟报点系统设计

单片机的多功能时钟对于公共场合,私人空间的每一天的生活都具有重要的功能意义,已经成为人们在日常生活中不可以缺少的部分。单片机应用于这个模块的设计是数字时钟。数字时钟是一种较为现实的数字电路设计,实现对于秒、分、时的整体设置。由于数字集成电路在实际的震荡电路中得到了广泛的应用,从而可以有效的保证时间的准确性,直观的对电子数字设备进行有效的控制。比机械数字控制具有更高的精准性,具有更长的使用寿命。钟表的数字计数可以合理的方便人们对于时间的参考和计量,加深时钟的计时功能,保证数字时钟的有效化应用过程,从而保证更加重要的社会实际意义。本文将针对AT89C51单片机进行核心内容的电路和温控设计,制作一个简单的电子时钟系统。     

面向5G智能电网的高精度时钟在线实时同步方法

针对5G智能电网的高精度时钟同步需求,提出一种主从节点时钟在线实时同步方法,并建立其数字实现模型。该方法采用一种由时差测量、时钟状态估计、环路滤波器和全数字时钟生成单元构成的时钟反馈控制环路。基于IEEE1588精确时间同步协议完成主从节点间的时差测量;根据时钟模型,建立时钟状态方程和观测方程,采用卡尔曼滤波对时钟状态进行估计;将时钟相位误差、频率误差作为一阶FLL辅助的PLL环路滤波器输入;环路滤波器输出控制量驱动调节从节点全数字时钟生成,以与主节点时钟保持在线实时同步。仿真结果表明,主从节点通信载噪比在65～95 dBHz范围内变化时,可实现主从节点间ns级的时钟同步精度。     

基于Multisim的数字钟电路仿真研究

数字钟是数字电子技术的综合应用,文中以数字钟设计为需求,分析了其工作原理,建立了基于Multisim的秒时基信号、数字钟计数显示仿真模型,给出了仿真波形,提出了理论分析、虚拟实验仿真和实际电路调试相结合的教学方法和基于工作过程即面向岗位的教学模式。实践证明,数字钟电路设计合理,新的教学方法,降低了对实验条件的要求,提高了学生的积极性,增强了学生的技能水平。     

基于EDA技术的数字钟设计与实现

为使数字钟从电路设计、性能分析到设计出PCB版(即印制电路版)图的整个过程能够在计算机上自动处理完成,从而缩短设计周期、提高设计效率、减小设计风险.本系统基于EDA技术的设计方法,提出一种采用P-MOS大规模集成电路LM8560作为计数译码的石英数字钟的设计方案,在Prote199SE软件平台下创建原理图和绘制印制电路...     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC     

A gallium-arsenide digital phase shifter for clock and controlsignal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components     

Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter

Rotary clock is a resonant clocking technique that delivers on-chip clock signal distribution with very low power dissipation. Since it can only generate clock signals with multiple phases that are spatially distributed, rotary clock is often considered not applicable to industrial very large scale integration (VLSI) designs. This paper presents the first rotary-clock-based nontrivial digital circuit. Our design, a low-power and high-speed finite-impulse response (FIR) filter, is fully digital and generated using CMOS standard cells in 0.18 mum technology. We have shown that the proposed FIR filter is seamlessly integrated with the rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. Simulation results demonstrate that our rotary-clock-based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gb/s. In comparison with the conventional clock-tree-based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. In addition, the peak current consumed by the rotary-clock-based filter is substantially lower by 40% on the average. Our study makes the crucial step toward the application of rotary clock technique to a broad range of VLSI designs.     

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS

We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated programmable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm/sup 2/. A new architecture is proposed which improves the authors' previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for application as a low-jitter clock multiplying unit in digital intensive systems on chip.     

基于Multisim 9的数字电子钟设计与仿真

数字电子钟广泛应用于各个公共场所,其电路设计的一般方法是连线多而杂,不便于理解其电路构成。利用中规模集成电路,设计了数字电子钟,由于采用了层次电路设计方法,将其分成各个单元电路设计成层次块,最后将各层次块连线成整机电路,连线美观,便于理解各单元电路功能,其整机电路功能也一目了然。