Hybrid evolutionary partitioning algorithm for heat transfer enhancement in VLSI circuits

In this paper, a new approach to improving the heat transfer in integrated circuits (ICs) is presented. It is based on improving the thermal conductivity of ICs by increasing the number of their external connections up to the level determined by the packaging standard. In order to attain this goal, a new hybrid evolutionary partitioning algorithm (HEPA) for circuits partitioning is introduced. The computations carried out for the chosen benchmarks show that HEPA is able to reach optimal solutions in the case of bipartitioning problem, and almost optimal in the case of k-way partitioning (k>2). The presented approach is especially dedicated for a flip chip interconnect technology which is used in contemporary ICs.     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

GA—BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

In this paper,the glitching activity and process variations in the maximum power dissipation estimation of CMOS circulits are introduced.Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view.The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02.Compared with the traditional Monte Carlo-based technique,the new approach presented in this paper is more effective.     

Frequency properties of on-die power distribution network in VLSI circuits

The local voltage fluctuations in the supply and ground grids triggered by on-die logic cell switching in VLSI devices have been experimentally studied. The results show that these fluctuations have a resonant-like form i.e., the on-die power grid should be described as an RLC circuit. The studies reveal that the active element (i.e., CMOS logic cell) affects the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). It is demonstrated that the frequency properties of the both grids are inter-related via the interconnecting active elements.     

Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8?V, 75°C demonstrate power reduction by 59.4% in case of 1?bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1?bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45?V applied in active mode improves the maximum operating frequency by 16% in case of 1?bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足日标延迟的条件下,利用托格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型.在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点.此模碰更适合全局瓦连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SoC的计算机辅助设计和集成电路优化设计.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.     

微分求积法求解高速大规模集成电路互连线的瞬态响应

本文将微分求积法（ＤＱ方法）应用于高速大规模集成电路互连线的瞬态模拟。ＤＱ方法是一种直接的数值方法，与差分和有限元法相比，它的计算量可以大大降低，具有较高的精度。ＤＱ方法的主要思想是将某坐标方向上的微分算子用该方向上一系列适当的离散点的函数值加仅逼近，将偏微分方程化为常微分方程或代数方程求解。ＤＱ方法用于高速大规模集成电路互连线系统的瞬态模拟非常有效，其适用范围也相当广泛。     

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-V_TH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-V_TH transistors in place of high-V_TH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-V_TH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.     

A Fast Macro-Model for Substrate Coupling and Ground Bounce Induced Substrate Noise Simulation in Mixed Signal VLSI

This paper discusses a novel substrate modeling technique for the simulation of substrate noise in mixed signal VLSI systems. This model yields to easy merger with the SPICE simulation netlist for the complete pre and post layout estimation of substrate noise effects in large mixed signal VLSI chips. Compared to previous numerous efforts in substrate noise modeling ranging from finite element methods (FEM) to boundary elements methods (BEM), this model, based on a finite sheet resistor slicing scheme also incorporates the effect of supply rail bounce due to bonding wire inductances, and, provides realistic estimates of substrate noise effects with a high degree of computational efficiency. Substrate noise simulations were done using a 0.18 m TSMC CMOS process technology using typical process parameters. A differential switched capacitor sample and hold circuit and a linear differential transconductor stage was used for the performance evaluation of this novel substrate model. Simulation results indicate a typical increase in Total Harmonic Distortion (THD) by atleast 6 dB due to the substrate noise effects, which corresponds to a performance loss by around 1-b precision. Also, the substrate noise effects are found to be proportional to the oversampling ratio (i.e., the digital clocking rate with respect to the input signal) and the net number of logic transitions at each register transfer instance in the mixed signal chip.     

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80× speed-up when comparing to electrical simulation.     

Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology.We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.     

Utilizing a novel root companding transform technique to reduce PAPR in OFDM systems

One major defect in orthogonal frequency division multiplexing systems is the high peak‐to‐average power ratio (PAPR) at the transmitter. The linear nonsymmetrical transform (LNST) technique, one of the companding transform (CT) techniques for PAPR reduction, offers excellent performance, but requires additional side information. In this paper, a new ‘root CT’ technique without additional side information is proposed, and it can reach a good trade‐off between the PAPR reduction and the bit error rate (BER). The theoretical analysis of the proposed root technique is also derived. The simulation results show that the proposed root CT technique can achieve more efficient PAPR reduction and better power spectrum density than those of the LNST technique. The BER of the proposed CT technique without additional side information is close to that of the LNST technique with additional side information when the AWGN or multipath fading channels are considered. Furthermore, the simulation results also demonstrate that the proposed technique offers better performance than that of the µ‐law technique over the AWGN and multipath fading channels. Copyright © 2010 John Wiley & Sons, Ltd.     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

A technique to improve network lifetime in mobile ad hoc networks

Energy is an important issue in mobile ad hoc networks (MANETs), and different energy‐aware routing mechanisms have been proposed to minimize the energy consumption in MANETs. Most of the energy‐aware routing schemes reported in the literature have considered only the residual battery capacity as the cost metric in computing a path. In this paper, we have proposed, an energy‐aware routing technique which considers the following parameters: (i) a cost metric, which is a function of residual battery power and energy consumption rate of participating nodes in path computation; (ii) a variable transmission power technique for transmitting data packets; and (iii) To minimize the over‐utilization of participating nodes, a limit is set on the number of paths that can be established to a destination through a participating node. The proposed scheme is simulated using Qualnet 4.5 simulator, and compared with Ad hoc On‐Demand Distance Vector (AODV) and Lifetime Enhancement Routing (LER). We observed that the proposed scheme performs better in terms of network lifetime and energy consumption. Copyright © 2014 John Wiley & Sons, Ltd.