A 2-V, low distortion, 1-GHz CMOS up-conversion mixer

A 1 GHz, very linear, CMOS up-conversion mixer is presented. The circuit is able to operate at a 2-V power supply. The topology has a true single-ended output stage which avoids the use of any balun. The total power consumption in both the mixers and the output stage is only 22 mW at 2 V. A profound analysis of the origins of distortion in the mixer has been performed. This study has resulted in the optimization of the linearity of the realized up-conversion mixer. The low power consumption, the low supply voltage, the high frequency performance, and the relatively large amplitude and low distortion single-ended off-chip output signal make the presented topology very suitable for wireless applications     

A 1-GHz active phase shifter with a ferroelectric varactor

An active phase shifter circuit implemented with discrete components is reported. The tuning element, a ferroelectric varactor, is a parallel plate capacitor with Ba/sub 0.5/Sr/sub 0.5/TiO/sub 3/ (BST) as the dielectric. The circuit consists of two bipolar junction transistors coupled with a feedback network, which contains the varactor and thus produces a transfer function that can be varied with a control voltage. The active nature of the circuit allows for signal gain, while the BST varactor provides a high-Q tuning element. This represents an improvement over strictly passive phase shifters with ferroelectric elements. Circuit simulation results are presented and compared with measured data from the implemented system. The network, even with markedly nonideal transistors, can provide a true all-pass response over the frequency band of interest (200-1100 MHz). The measurement results demonstrate an analog tunability of about 100/spl deg/ with a gain variation of about 0.6 dB at I GHz when using a BST capacitor with a tunability of 2.75:1.     

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digitalwireless communication

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC consisting of receive, transmit, and local oscillator (LO) sections is presented. The transmit section achieves an unwanted sideband suppression of -43 dBc, LO leakage of -59 dBc, and third-order spurious rejection of -70 dBc. The transmit output noise level is -165 dBc/Hz at a 20-MHz offset from the carrier. The on-chip very high-frequency oscillator has a phase-noise level of -106 dBc/Hz at 100-kHz offset when operating at 800 MHz. The receive section has 36 dB of gain with 36 dB of gain range in 12-dB steps. The transceiver IC has been fabricated using a 25-GHz f_t silicon bipolar process and is designed to operate over a supply-voltage range of 2.7-5.0 V     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator

A 2-GHz Si-bipolar direct-conversion quadrature modulator with a wide bandwidth is described. It operates at a low supply-voltage of 2 V and features a “current-folded” double-balanced mixer with a two-stacked-transistor configuration, and a tunable RC/CR 90° phase shifter that reduces the amplitude imbalance and the phase error over a wide bandwidth (0.8 to 2 GHz). The modulator is implemented using 18-GHz Si-bipolar technology and dissipates only 68 mW at 2 V. The image ratio at 2 GHz is about -37 dBc, corresponding to a phase error of 1.6°. Moreover, both second-order and third-order products, and local signal leakage are less than -40 dBc     

A 2-V 2-GHz BJT variable frequency oscillator

A new LC-tuned negative-resistance variable-frequency oscillator (VFO) is described. Frequency tuning is accomplished by using a variable-impedance converter (VIC) to simulate the varactor function. A negative-impedance converter provides the necessary negative resistance for oscillation and also functions as the voltage level shifters for the VIC. A low-voltage translinear circuit is used to linearize the tuning characteristic of the VFO. Implemented in a 0.8 μm 12 GHz f_T BiCMOS technology, the VFO has a tuning range from 1.55 to 2.02 GHz, while consuming 15 mA from a -2 V supply     

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

一种3.3 V 2-GHz CMOS低噪声放大器

介绍了一个针对无线通讯应用的2-GHz低噪声放大器(LNA)的设计。该电路采用标准的0.6μm CMOS工艺，电源电压为3．3V，设计中使用了多个片上电感。对低噪声放大器的噪声进行了分析，模拟结果显示，该电路能提供18dB的正向增益(S21)及良好的反向隔离性能(S12为-44dB)，功耗为33．94mW，噪声系数为2．3dB，IIP3为-4．9dBm。     

A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13-/spl mu/m CMOS technology

A broadband microwave/millimeter-wave (MMW) Gilbert-cellmixer using standard 1P8M 0.13-/spl mu/m complementary metal oxide semiconductor (CMOS) technology is presented in this letter. Two radio frequency (RF) transformer baluns are used in RF-and local oscillator (LO)-ports to convert single-ended signals to differential signals. Thin film microstrip line is employed for the matching networks and transformer design. This mixer has a conversion gain of better than 5dB from 9 to 50GHz. Between 5 and 50GHz,the RF- and LO-to-intermediate frequency (IF) isolations are better than 40dB. The RF-to-LO and LO-to-RF isolations are all better than 20dB. To the authors' knowledge, this is the first CMOS Gilbert-cell mixer operating to MMW frequency to date.     

A low-voltage ultra-wideband down-conversion mixer with improved power conversion gain

This article presents a wideband mixer using a TSMC 0.18?µm complementary metal-oxide semiconductor technology process for ultra-wideband (UWB) system applications. The measured 3-dB radio frequency (RF) bandwidth is from 3 to 8.4?GHz with an intermediate frequency of 10?MHz. The measurement results of the proposed mixer achieve 8.1?dB average power conversion gain ?5?dBm input third-order intercept point (IIP3) at 7.4?GHz and 12.4–13.3?dB double side band noise figure. The total dc power consumption of this mixer including output buffers is 3.18?mW from a 1?V supply voltage. The output current buffer consumption is about 2.26?mW with an excellent local oscillator-RF isolation of up to 40?dB at 5?GHz. The article presents a mixer topology that is greatly suitable for low-power operation in UWB system applications.     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 1.9-GHz CMOS VCO with micromachined electromechanically tunablecapacitors

This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-μm CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively     

A 1.8-V 6/9-GHz reconfigurable dual-band quadrature LC VCO in SiGe BiCMOS technology

This paper presents a dual-band voltage-controlled oscillator (VCO) that can be reconfigured between 6- and 9-GHz frequency bands. It comprises a 6-GHz LC-tuned VCO, two 1/2 dividers, two mixers, and two 3-GHz notch filters. The 9-GHz output is generated based on the analog frequency multiplication method by mixing the 6-GHz VCO output with its divide-by-two signal. The VCO, implemented in a 0.18-/spl mu/m SiGe BiCMOS technology, achieves a fast reconfiguration time of 3.6 ns. The measured VCO phase noises are -106 and -104 dBc/Hz at 1-MHz offset for 6- and 9-GHz modes, respectively, while draining 10.8 mA from a 1.8-V supply.     

A 1-GHz CMOS up-conversion mixer

A high-frequency linear MOS mixer topology is presented for the implementation of a 1-GHz up-conversion mixer in a standard 0.7-μm CMOS technology. The high output bandwidth has been achieved by the development of an nMOS-only current amplifier that converts the modulated current of the nMOS mixing transistor biased in the linear region to the RF output voltage     

A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply     

A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications

This paper presents a semi-active in-phase/quadrature inductor-less down-conversion mixer. The mixer consists of an active trans-conductance stage, a passive current switching stage, and a trans-impedance stage. A complementary input architecture has been used to increase the trans-conductance for a given bias current. An on-chip prescaler is added to provide the balanced LO signals, while the CMFB circuit in trans-conductance stage is designed to enhance linearity. The chip was achieved in a 0.13???m CMOS technology. It features 5?dB conversion gain over a broad range from 800?MHz to 2.1?GHz, which supports Chinese TD-SCDMA/RFID standards simultaneously. The maximum IIP2 is +76?dBm at 2.1?GHz and suitable for application within a direct-conversion receiver.     

10-GHz Si bipolar amplifier and mixer ICs for coherent opticalsystems

Using a 30-GHz f_T silicon bipolar process, 10-GHz amplifier and mixer ICs for a multigigabit-per-second coherent optical-fiber communication system were fabricated. The dual-feedback amplifier with triple Darlington achieves a 10-GHz bandwidth and 20-dB gain. The Gilbert-cell mixer operates up to 10 GHz with a 10-dB conversion loss. The simulation technique, used for the design of these ICs includes an improved interconnect line model for the high-frequency region. The 10-GHz amplifier has a 1-mm² chip size and 210-mW power dissipation. The mixer has 2-mm² chip size and 550-mW power dissipation     

A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.     

A 4.3-GHz VCO with 2-GHz tuning range and low phase noise

A voltage-controlled oscillator (VCO) based on double cross-coupled multivibrator structure with a center frequency of 4.3 GHz and a tuning range of 2 GHz has been designed and implemented in standard 0.35 μm BiCMOS technology. The measured phase noise is 113 dBc/Hz at 600-kHz offset frequency from the carrier. The VCO draws 14.6 mA from the 2.5-V supply     

采用O.18μm CMOS RF模型的高线性度降频混频电路的设计

介绍了降频混频电路的电路结构及其工作原理,并且着重分析了一种高线性度的实现方法.电路采用了0.18um CMOS RF模型,通过仿真,得出了令人满意的结果.