CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.     

A very high precision 500-nA CMOS floating-gate analog voltage reference

A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.     

A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference scheme

We present a microcontroller having a 0.5-/spl mu/A standby current on-chip regulator. To break through the area overhead problem which a conventional regulator scheme suffers from to achieve small standby current, we propose a dual-reference scheme in which one voltage reference circuit is provided for active mode and another voltage reference circuit is provided for standby mode. For the voltage reference circuit for standby mode, a resistor-free circuit was used to achieve small current consumption without occupying large area. The microcontroller was fabricated in a 0.18-/spl mu/m CMOS process. The implementation and measurement results show that the dual-reference scheme achieves 0.5-/spl mu/A current consumption of the regulator in standby mode with 50% smaller area than the conventional scheme. The measured standby current of the whole chip was 2.0 /spl mu/A.     

MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.     

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.     

Low-power low-voltage reference using peaking current mirror circuit

A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.     

CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V

A CMOS bandgap voltage reference (BVR) circuit is proposed that operates at power supply voltages down to 0.6 V. The BVR is designed in a commercially available 0.13 /spl mu/m digital CMOS technology. No analogue process options are required.     

CMOS digital duty cycle correction circuit for multi-phase clock

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50/spl plusmn/0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 /spl mu/m CMOS technology is used in this work.     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

对电源及温度不敏感的电流可调的CMOS电荷泵电路的设计

设计了一种电流可调的CMOS电荷泵电路,其中采用了带隙基准源、低drop-out调压器及电容式直流-直流电压升压器为电荷泵电路提供电源电压,此电压不受外部供电电压及温度变化的影响;同时,电荷泵电路中的参考电流源本身也对温度变化不敏感.电路设计采用0.18μm 1.8V标准的数字CMOS工艺.模拟结果表明电路性能令人满意.     

An analog front end for 2400-bit/s split-band full-duplex modems

An analog front-end LSI for 1200/2400 full-duplex modems which conform to CCITT V.22. and Bell 212A is described. The chip includes A/D and D/A converters, bandlimiting filters, delay equalizers, AGC circuit, tone generator, multipurpose low-pass filter, and voltage reference generator. The chip is fabricated by a 5-/spl mu/m CMOS process, and chip size is 6.50 mm/spl times/6.37 mm. The circuit operates from +5.0-V and -5.0-V power supplies. Typical power consumption is 100 mW.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

A low-voltage CMOS bandgap reference

The CMOS bandgap voltage reference described here uses the bipolar substrate-transistor and the bipolar-like source-to-drain transfer characteristics of MOS transistors in weak inversion to implement a voltage source that is proportional to absolute temperature (PTAT). A first version of PTAT source is derived from a circuit described previously. A second version is based on a novel cell that can be stacked to obtain the desired voltage. Both versions operate down to 1.3 V with a current drain below 1 /spl mu/A. A stability of 3 mV over 100/spl deg/C has been obtained with a few nonadjusted samples. Experimental results suggest some possible improvements to extend this stability to every circuit.     

A true-1-V 300-/spl mu/W CMOS-subthreshold log-domain hearing-aid-on-chip

This paper presents a true very low-voltage low-power complete analog hearing-aid system-on-chip as a demonstrator of novel analog CMOS circuit techniques based on log companding processing and using MOS transistors operating in subthreshold. Low-voltage circuit implementations are given for all of the required functions including amplification and automatic gain control filtering, generation, and pulse-duration modulation. Based on these blocks, a single 1-V 300-/spl mu/A application specific integrated circuit integrating a complete hearing aid in a standard 1.2-/spl mu/m CMOS technology is presented along with exhaustive experimental data. To the authors' knowledge, the presented system is the only CMOS hearing aid with true internal operation at the battery supply voltage and with one of the lowest current consumptions reported in literature. The resulting low-voltage CMOS circuit techniques may also be applied to the design of A/D converters for digital hearing aids.     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.     

A high-speed 64K CMOS RAM with bipolar sense amplifiers

A TTL-compatible 64K static RAM with CMOS-bipolar circuitry has been developed using a 1.2-/spl mu/m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mW active power and 100 nW standby power. A CMOS six-transistor memory cell is used. The cell size is 18/spl times/20 /spl mu/m, and the chip size is 5.95/spl times/6.84 mm. The n-p-n transistors are used in the sense amplifiers, voltage regulators, and level clamping circuits. The bipolar sense amplifiers reduce the detectable bit line swing, thus improving the worst-case bit line delay time and the sensing delay time. In order to reduce the word line delay, the MoSi layer, which has 5 /spl Omega//sheet resistivity, was used for the gate material. The n-well CMOS process is based on a scaled CMOS process, and collector-isolated n-p-n transistors and CMOS are integrated simultaneously without adding any extra process steps and without causing any degradation of CMOS characteristics. The n-p-n transistor has a 2-GHz cutoff frequency at 1 mA collector current.     

CMOS exponential function generator

A new CMOS exponential function generator is presented. The proposed circuit is compact, with low power and wide dynamic range. The proposed circuit has been fabricated in a 0.50 /spl mu/m CMOS process. Experimental results show that the output range of the proposed exponential function generator can be more than 15 dB with the linear error less than /spl plusmn/ 0.5 dB. The supply voltage is /spl plusmn/ 1.5 V and the power dissipation is less than 0.4 mW. Experimental results are given to demonstrate the proposed circuit.