Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Observation of reduced boron penetration and gate depletion forpoly-Si0.8Ge0.2 gated PMOS devices

Poly-Si_0.8Ge_0.2-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si _0.8Ge_0.2-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO₂ interface and therefore improved PDE were also found in boron-implanted poly-Si_0.8Ge_0.2-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si_0.8Ge_0.2 gate technology with regard to the tradeoff between boron penetration and poly-gate depletion     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

Preparation of SiO2-B2O3 glass forPANDA optical fibre from colloidal sol-gel process

SiO₂-B₂O₃ glass for the PANDA optical fibre is prepared from the colloidal sol-gel process. The preparation of SiO₂-B₂O₃ glass is through the gellation of fumed silica dispersed in water containing boric acid. Two processes to dry the gel are examined, and freeze-drying is selected as the better drying method. The process produces a dried gel without cracks and with a uniform distribution of boron oxide concentration. The dried gel is sintered into glass     

Thickness dependence of boron penetration through O2 and N2O-grown gate oxides and its impact on threshold voltagevariation

We report on a quantitative study of boron penetration from p⁺ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O₂ or N₂O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N_B, for thicknesses other than those measured. We find that the minimum t_ox required to inhibit boron penetration is always 2-4 nm less when N₂O-grown gate oxides are used in place of O₂- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t_ox, incremental variations in oxide thickness result in a large variation in N_B , leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10¹¹ cm^-2     

The effect of silicon gate microstructure and gate oxide process onthreshold voltage instabilities in p+-gate p-channel MOSFETswith fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V_TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V_TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO₂/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V_TP shift     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

Impurity barrier properties of reoxidized nitrided oxide films foruse with P+-doped polysilicon gates

The ability of thin reoxidized nitrided oxide (ONO) gate dielectrics formed by rapid thermal processing to act as a barrier to boron penetration resulting from p⁺ poly gate processing are investigated. Measurements comparing the threshold voltage instability of capacitors fabricated with BF₂ implanted poly gates subjected to various postgate thermal cycles have been performed. The ONO gate dielectrics are found to be an excellent impurity barrier to boron diffusion, even in the presence of fluorine. The extent of the nitridation is also found to affect the diffusion barrier properties, with the highest temperature nitridations forming the best barriers. Reoxidation of the nitrided films reduces the barrier properties somewhat, but improvement is still observed over SiO₂     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Flatband voltage shift in PMOS devices caused by carrier activationin p+-polycrystalline silicon and by boron penetration

After discovering that the annealing-time dependence of the flatband voltage shifts of a p⁺-polysilicon gate MOS diode can be attributed to boron activation in polysilicon instead of boron penetration through gate M₂, we proposed a boron activation model for polysilicon in which the carrier activation is related to the grain size of the polysilicon. Using this model, we analyzed the characteristics of pMOSFETs with polysilicon gates of different grain sizes and found that they depend on the grain size, as expected. Using the model, we quantitatively identified process windows for p⁺-polysilicon gate pMOSFETs, assuming that enough boron is activated in the polysilicon without the boron penetrating through the gate SiO₂     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

MOS characteristics of NH3-nitrided N2O-grownoxides

The technique of NH₃ nitridation of N₂O oxides is proposed and demonstrated for increasing nitrogen concentration in N₂O oxides so as to improve the resistance to boron penetration, without any adverse effects on electrical and reliability properties. Results show that NH₃-nitrided N₂O oxides exhibit excellent electrical (low fixed charge) and reliability (smaller charge trapping and suppressed interface state generation) properties, with an additional advantage of significantly improved resistance to boron generation. This technique may have a great impact on deep-submicrometer dual-gate CMOS technology     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

SiO2 masking against phosphorus diffusion using a P2O5 source

The masking of silicon against deep P₂O₅ diffusion by a 1-μ thick SiO₂ layer has been investigated. One aspect of masking failure has been related to mounds of phosphorus silicate glass, grown on the oxide during the P₂O₅ deposition, causing spot penetration of phosphorus through the oxide and into the silicon. Such spots can increase in density, diameter and depth during the subsequent diffusion. They link up and form a continuous, but not uniform n-type layer under the oxide. Residual water vapour in the deposition systems and particle deposits on wafers during washing have been shown to be the factors that contribute to the growth of mounds.     

BF2 and boron double-implanted source/drain junctionsfor sub-0.25-μm CMOS technology

A double implant source/drain junction formation process using BF ₂ and boron is proposed for PMOSFET in sum-0.25-μm CMOS technology. Compared to the more conventional, single implant processes using BF₂, the double implant process with downscaled BF₂ implant energy offers the advantages of lower junction capacitance, less boron penetration, thinner gate oxide, and wider process window, as experimentally demonstrated     

Electrical characterization of the Si substrate in magneticallyenhanced or conventional reactive-ion-etch-exposed SiO2/p-Sistructures

The authors explore the silicon substrate damage produced by Cl ₂- and HBr-based reactive ion polycrystalline silicon overetches used in the definition of polycrystalline-Si/SiO₂/single-crystal-Si structures. The damage-caused traps, examined by means of deep-level transient spectroscopy, in the p-type Si are found to have concentrations that can exceed one tenth that of the boron dopant, and are detectable as far as ~10 μm from the SiO₂/Si interface. The concentration and depth of these traps are shown to depend on the polycrystalline Si overetch selectivity, on the initial oxide thickness, and on the magnetic field strength, as well as on the presence of hydrogen