SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

双台阶式埋氧SGOI自加热效应的数值研究

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator(SGOI) n-type metal-oxide-semiconductor field-effect transistors(nMOSFETs),this paper proposes a novel device called double step buried oxide(BOX) SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from...     

射频功率HBT自加热效应及补偿方法

从器件I-V特性的角度,表征了射频功率异质结双极晶体管(HBT)的自加热效应。研究了器件热阻、工作电压、电流增益、发射结价带不连续性(ΔEV)等诸多因素对器件I-V特性的影响。进而研究了为补偿自加热效应所加镇流电阻对热稳定性的改善情况,给出了器件热稳定所需最小镇流电阻(REmin)与这些因素的关系。结果表明,HBT的REmin要小于同质结双极晶体管(BJT)的REmin,因此,射频功率HBT将有更大的输出功率、功率增益和功率附加效率(PAE)。     

SOI LDMOS晶体管的自加热效应

与常规体硅器件相比,SOI器件由于其独特的结构,常常会产生较严重的自加热效应,影响器件的可靠性.文中阐述SOI LDMOS功率晶体管中的自加热现象,研究了自加热效应产生的机理,在不同的结构和工艺参数下自加热效应的研究进展,以及减弱自加热效应的方法.研究证明采用新材料,结构可对同加热效应起到有效抑制作用提高了件的可靠性.     

应用于硅基等离子天线的LPIN二极管的自加热效应

介绍了LPIN二极管及其在硅基等离子天线方面的应用,从理论上分析了LPIN二极管自加热效应及其对本征区载流子浓度的影响.仿真分析了不同SOI埋层材料对LPIN二极管本征区载流子浓度的影响.仿真结果显示,LPIN二极管的自加热效应会降低其本征区载流子浓度,通过改变埋层的材料,增加埋层的热导率,可以减弱自加热效应,从而增加本征区载流子浓度,提高硅基等离子天线效率.     

一种考虑自热效应的AlGaN/GaN HEMT大信号模型

当AlGaN/GaN HEMT输出高功率密度时,器件沟道温度的升高将引起电流的下降(自热效应).提出了一种针对AlGaN/GaN HEMT改进的大信号等效电路模型,考虑了HEMT自热效应,建立了一种改进的大信号I-V特性模型,仿真结果与测试结果符合较好,提高了大信号模型的精度.     

新型SON器件的自加热效应

分析了自加热效应对SON器件性能的影响,并与SOI器件进行了比较.提出构造散热通路的方法来抑制SON器件的自加热效应,分析了不同通路情况对自加热效应的抑制程度.还对散热性能较好的具有不连续空洞埋层的SON器件进行了研究,并分析了空洞大小和横向位置偏差对器件性能的影响,为器件结构设计提供了指导.     

新型SON器件的自加热效应

分析了自加热效应对SON器件性能的影响,并与SOI器件进行了比较．提出构造散热通路的方法来抑制SON器件的自加热效应,分析了不同通路情况对自加热效应的抑制程度．还对散热性能较好的具有不连续空洞埋层的SON器件进行了研究,并分析了空洞大小和横向位置偏差对器件性能的影响,为器件结构设计提供了指导．     

深结短沟道MOS晶体管准二维阈值电压模型

提出了一个新的短沟道MOS晶体管表面势的准二维解析模型。不同于经典模型,该模型对沟道耗尽层横向剖分,由高斯定理导出沟道耗尽层电势的一维微分方程,方程考虑了漏、源的横向电场对沟道耗尽层厚度的影响。求解方程得到了耗尽层厚度与表面势的关系函数,由此得出了一个包含有沟道长度的阈值电压公式。通过MEDICI软件对多种不同参数的MOS晶体管进行了仿真,此模型计算结果与MEDICI仿真数据吻合较好,比电荷分享模型精度高。     

CoolMOS MOSFET

英飞凌科技推出下一代高性能金属氧化物半导体场效应晶体管（MOSFET）600VCoolMOSC6系列。有了600VCoolMOSC6系列器件,诸如PFC（功率因数校正）级或PWM（脉宽调制）级能源转换产品的能源效率可得到大幅提升。     

Compensated MOSFET devices

The turn-on and conduction mechanisms of a p-channel compensated MOSFET are discussed. Depending on the implantation and back-bias conditions, two distinct modes of operation occur, each with its own characteristic threshold voltage and conductance relations. In addition, major factors influencing punch-through and the associated subthreshold characteristics have been taken into account. The effect of inversion in the compensating p-layer on the gate capacitance is shown. Experimental data verify the theoretical results presented. Consequences of typical device properties for CMOS modelling are discussed.     

非对称轻掺杂漏(LDD)MOSFET

提出并制作了一种仅有漏端轻掺杂区的MOSFET新结构──非对称LDD MOSFET。它与通常LDD MOSFET相比,抑制热载流子效应的能力相同,源漏串联电阻降低40％左右,线性区和饱和区的跨导分别增加50％和20％左右。用该器件制作的CMOS电路,其速度性能优于通常LDD MOSFET制作的同样电路。     

MOSFET doping profiling

An automated technique was developed for rapid measurement of MOSFET channel doping profiles. The technique is based on the well-known relationship between the device threshold voltage and substrate bias. It uses only DC voltage measurements and is not subject to the limitations of conventional capacitance-voltage (C-V) methods. An operational amplifier feedback circuit is used to determine the threshold voltage automatically as the substrate bias voltage is varied. Doping profiles determined with this technique agree very well with those obtained from C-V and from spreading resistance measurements, as well as with those predicted by SUPREM-3. The devices were fabricated with processes representing two generations of CMOS technology. The doping concentrations, channel implants, and gate oxide thicknesses varied significantly between the two, allowing the assessment of the accuracy of doping profile extraction techniques for devices representing a wide performance range     

Novel split-gate MOSFET

A new type of split-gate MOSFET (SG-MOSFET) is described that employs a complementary poly-Si-gate buried-channel MOS process. In this configuration, complementary SG-MOS's provide higher transconductance and a one-order smaller magnitude of channel-length modulation than with conventional buried-channel MOSFET's. Moreover, there is no requirement for additional mask steps. Four-times higher packing density was also obtained in a differential amplifier application.     

Ultra-small punchthrough MOSFET

A design for an ultra-small MOSFET is presented. MOSFETs with submicron channel lengths (L 0.25 μm) that operate with controlled punchthrough current are analyzed by two-dimensional numerical modeling. Current-voltage characteristics for subthreshold, nonsaturated and saturated regions of operation were obtained at various temperatures for devices of different channel length. The results indicate that device current is due to barrier-limited, space-charge-limited and surface-inversion conduction processes.     

Pi-Gate SOI MOSFET

This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a “Π-gate” or “Pi-gate” MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET     

MOSFET memory circuits

Metal-oxide-semiconductor first effect transistors (MOSFETs) are currently being used in a variety of memory applications. The requirements of memory usage and the characteristics of MOSFET devices and technology have led to a number of unique circuits for these applications. Organization and design considerations of memory systems using MOSFET devices are reviewed, and examples of specific circuits are presented and analyzed. These include random access cells, shift registers, read only storage, and on-chip support circuits; both complementary and noncomplementary circuits are discussed.