CMOS自对准硅化钛工艺研究

形成硅化物的技术有多种：蒸发,溅射和化学气相沉积。文中对单靶溅射钛膜进行了研究。采用两步快速热退火工艺形成ＴｉＳｉ２,通过实验,得出了ＣＭＯＳ自对准硅化钛的工艺条件。     

Film Properties of MoSi/sub 2/ and Their Application to Self-Aligned MoSi/sub 2/ Gate MOSFET

Molybdenum silicide (MoSi/sub 2/) gate technology has been extensively investigated in conjunction with MOS device performance and reliability. Features of the MoSi/sub 2/) gate technology are to realize a low resistivity of 1 X 10/sup -4/ Omega · cm for both gate and interconnection, and to give rise to higher reliability under both positive and negative bias stress of 2 MV/cm at 250/spl deg/C. Problems on the ohmic contact between MoSi/sub 2/ and single-crystal substrates are not completely solved yet, particularly when the device is processed at high temperature after MoSi/sub 2/ deposition.     

Composite TiSi/sub 2//n+ Poly-Si Low-Resistivity Gate Electrode and Interconnect for VLSI Device Technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi/sub 2/ polycide gate. A coevaporated TiSi/sub 2/ polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi/sub 2/ because of lower oxygen contamination. The coevaporation technique to form TiSi/sub 2/ polycide with a sheet resistivity of 1 Omega/square (bulk resistivity of 21 µOmega · cm) is described. Anisotropic etching of nominally 1-/spl mu/m lines with a 15 : 1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi/sub 2/ polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

应力技术改善CMOS器件性能研究进展

随着集成电路技术的快速发展,等比例缩小技术已经不能满足摩尔定律,应变硅金属氧化物硅场效应晶体管(MOSFET)技术成为后硅时代研究的热点。应变硅技术通过拉伸或压缩硅晶格达到器件尺寸不变的情况下,可提高器件性能的目的,同时应变硅技术与传统硅工艺兼容,节约了生产成本。对于应变硅互补金属氧化物硅晶体管(CMOS)器件的性能以及可靠性问题的研究也日益增加。本文通过介绍几种常用的应变技术(应力记忆技术(SMT),锗化硅技术(SiGe),接触孔刻蚀阻挡层(CESL))的应变机理、材料性能和工艺条件对应力技术的影响来探讨以后应力技术的发展趋势。     

兼容标准CMOS工艺的高压器件设计与模拟

在Synopsys TCAD软件环境下,模拟实现了与0.5μm标准CMOS工艺兼容的高压CMOS器件,其中NMOS耐压达到108V,PMOS耐压达到-69V.在标准CMOS工艺的基础上添加三块掩膜版和五次离子注入即可完成高压CMOS器件,从而实现高、低压CMOS器件的集成.此高压兼容工艺适用于制作带高压接口的复杂信号处理电路.     

兼容标准CMOS工艺的高压器件设计与模拟

在Synopsys TCAD软件环境下,模拟实现了与0 .5 μm标准CMOS工艺兼容的高压CMOS器件,其中NMOS耐压达到10 8V,PMOS耐压达到- 6 9V.在标准CMOS工艺的基础上添加三块掩膜版和五次离子注入即可完成高压CMOS器件,从而实现高、低压CMOS器件的集成.此高压兼容工艺适用于制作带高压接口的复杂信号处理电路.     

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO/sub 2/ gate dielectrics

Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.     

深亚微米/纳米CMOS器件离子蚀刻新技术

综述了制备深亚微米/纳米CMOS器件的离子蚀刻新技术:考夫曼(Kaufman)离子铣蚀刻、氟基气体多晶硅蚀刻、氯基或溴基气体硅深蚀刻、电子回旋共振(ECR)蚀刻系统和电感耦合等离子体蚀刻器(ICPE)等,并对比分析了上述蚀刻技术各自的优缺点及其应用要点.     

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

In the present work, a high aspect ratio process (HARP) using a new O₃/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed     

Investigation of NiSi and TiSi as CMOS gate materials

NiSi is a promising new candidate for CMOS gate metal material because its workfunction can be adjusted by the implantation of dopants into the silicon before silicidation. In this report, NiSi and TiSi are studied, and the work functions of each are found to be adjustable over a wider range than previously published. This range covers the work function values required to achieve correct threshold voltages (V/sub t/) for both deep-scaled bulk CMOS and fully depleted, silicon-on-insulator MOSFETs. The influence of these silicides on the gate oxide and interface quality is also examined thoroughly via measurements of capacitance, minority carrier mobility, and gate-leakage current. While no degradation of the interface is observed with NiSi gates, TiSi gates generate interface traps and significantly degrade transistor device performance. With all the merits of a metal gate and no apparent degradation of interface quality, NiSi can be integrated with minor modification into a standard CMOS process and is a promising gate metal material for future CMOS technology generations.     

薄膜亚微米CMOS／SOS工艺的开发及其器件的研制

本文较为详细地介绍了薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺技术的开发过程，薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺主要包括双固相外延，双层胶光刻形成亚微米细线条硅栅、Ｈ２－Ｏ２合成氧化薄栅氧化层以及快速退火等新的工艺技术，利用这套工艺成功地研制出了高性能薄膜来微米ＣＭＯＳ／ＳＯＳ器件和门延迟时间仅为１７７ｐｓ的１９级ＣＭＯＳ／ＳＯＳ环形振荡器，与厚膜器件相比，薄膜全耗尺器件和电路的性能得到了明显的提高。     

短沟道铝栅CMOS器件及工艺研究

利用计算机模拟软件Tsuprem4、Medici以及流片实验开发了短沟道铝栅CM0S器件及其工艺流程.对铝栅1.5μm短沟道CMOS工艺进行器件结构、工艺和电气性能等参数的进行了大量的模拟和流片实验,最后在提出的工艺平台上成功流水了1.5μm铝栅CMOS流片测试的阈值电压为士O.6V,击穿达到11V,各项指标参数的模拟与实际测试误差在5%以内,器件的各项指标达到了量产的要求.     

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 $ muhbox{m}^{2}$. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 $hbox{rm{AA}}$, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.      

InP/InGaAs SHBT器件自对准结构设计和工艺实现

从InP湿法腐蚀各向异性特性实验出发,利用传统的基极-发射极自对准工艺和改进的基极-发射极工艺制作了两种InP/InGaAs SHBT自对准结构,比较了两种自对准工艺对减小基极与发射极台面间距的效果,为制作高频率特性InP/InGaAs SHBT提供了工艺途径.     

InP/InGaAs SHBT器件自对准结构设计和工艺实现

从InP湿法腐蚀各向异性特性实验出发，利用传统的基极-发射极自对准工艺和改进的基极-发射极工艺制作了两种InP/InGaAs SHBT自对准结构，比较了两种自对准工艺对减小基极与发射极台面间距的效果，为制作高频率特性InP/InGaAs SHBT提供了工艺途径.     

InP/InGaAs SHBT器件自对准结构设计和工艺实现

从InP湿法腐蚀各向异性特性实验出发,利用传统的基极-发射极自对准工艺和改进的基极-发射极工艺制作了两种InP/InGaAs SHBT自对准结构,比较了两种自对准工艺对减小基极与发射极台面间距的效果,为制作高频率特性InP/InGaAs SHBT提供了工艺途径.