Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures

The low temperatures current-voltage characteristics of N-channel MOS transistors have been analysed. An excess drain current is observed for intermediate values of drain voltage. This anomalous drain current is explained in terms of substrate freeze-out, since at very low temperatures the MOS structure has a type of floating substrate potential within the depletion region. Due to the increase of the majority carrier current, flowing through the substrate to the source at increasing drain voltage, this substrate potential increases and causes a change of threshold voltage. This change is observed in the current-drain voltage characteristics of the MOSFET. Various experiments, such as measurements of substrate current, effects of temperature, gate and substrate voltages, support this interpretation. MOS transistors with various geometries and various dopings are analysed.     

Equivalent input spectrum and drain current spectrum for 1/ƒ noise in short channel MOS transistors

Flicker noise in MOS transistors can be evaluated by measuring the spectrum S_ID of the drain current fluctuation or the spectrum Sve of an equivalent gate fluctuation. We show here that experimental variations of are in good agreement with g_m² by considering a model of the transconductance g_m which takes into account the variations of the channel carriers mobility with the surface electric field. The model agrees with the experimental results obtained on short channel MOS transistors which exhibit large variations of mobility with the gate voltage. The validity of physical interpretations of noise data on MOS transistors is examined.     

Accurate two sections model for MOS transistor in saturation

In this paper an experimental and theoretical analysis of the characteristics of MOS transistors in saturation is presented. The experimental study of the drain current and output resistance brought to light a hitherto undescribed property of the product (R_D.I_D)². Based on this property a model is developed in which the channel is assumed to be divided into two regions. This model enables one, by means of a simple algorithmic calculation, to simulate the dependence of the drain current or of the output resistance as a function of the bias voltages. The continuity of these characteristics with those provided by the approximation of the gradual region is ensured. The experimental methods of determining the parameters acting on the saturation resisrance, as well as their main properties, are described.     

High threshold voltages in small geometry mos transistors due to edge contamination

A new type of high threshold problem in small geometry MOS transistors is identified and characterized. The origin of the problem lies in processing irregularities which produce a contamination charge only at the edges of the gate oxide region. Such contamination is introduced by an inadequate rinsing procedure after gate oxide definition. This type of an edge contamination is shown both experimentally and theoretically to create a change in the threshold voltage, transconductance and the shape of the I_D-V_GS transfer curve. The I_D-V_GS transfer characteristics for such a condition is derived theoretically using a Fourier series expansion method to solve Poisson's equation for the surface potential. This is then used to determine the variation in threshold voltage across the width of the gate and subsequently to predict the transfer characteristic. Comparison of experimental and theoretical results shows excellent agreement.     

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the ID-VDcharacteristics could be simulated by computer model based on the physical effects.     

Temperature selectivity of the radiation effect on silicon MOS transistors

Using the technique of the subthreshold currents of metal-oxide-semiconductor (MOS) transistors in the temperature range of 290–450 K, the effect of the temperature conditions of X-ray irradiation on the kinetics of the parameters U _th and D _it of silicon MOS transistors with a channel length of 2–10 μm is studied. It was shown that, according to the parameters under study, the radiation sensitivity of transistors decreases at irradiation temperatures above 360 K (the temperature of the low-temperature maximum in the spectrum of a thermostimulated depolarization (TSD) transistor) and reaches a maximum near 430 K (corresponding to the high-temperature maximum). The results obtained are interpreted from the standpoint of a model of the existence of two carrier trap types, the redistribution of electrically active Na⁺, K⁺, Li⁺, and H⁺ ions between them under irradiation, and the effect of the partial neutralization of charges at the interface.     

3D real-space quantum transport simulation of nanowire MOS transistors: Influence of the ionized doping impurity

We report a numerical study of both donor- and acceptor doping impurity effects in the quantum transport of silicon nanowire metal-oxide-semiconductor (MOS) transistors. The code is based on a full three-dimensional (3D) real-space non-equilibrium green function (NEGF) formalism self-consistently coupled with the 3D Poisson equation. The general results show that the influence of an impurity strongly depends on its type. Indeed, an acceptor or a donor will create a repulsive or attractive potential, giving rise to tunneling effect or resonances, respectively. Our calculations analyze the impact on electron density, transmission coefficient and drain current (I_D) which undergoes variations up to 50%. This pinpoints the importance of intrinsic fluctuations due to doping in ultimate nano-transistors whose magnitude cannot be neglected in the next generations of integrated circuits.     

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage (C-V) characteristics of these devices.Techniques are presented for determining the impurity profile of the buried layer from the low frequency C-V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C-t) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.     

Deposition of HfO2 on InAs by atomic-layer deposition

Metal–oxide–semiconductor (MOS) capacitors are formed on bulk InAs substrates by atomic-layer deposition (ALD) of HfO₂. Prior to film growth, InAs substrates receive a wet-chemical treatment of HCl, buffered HF (BHF), or (NH₄)₂S. Hafnium dioxide films are grown using 75 ALD cycles with substrate temperatures of 100, 200, and 300 °C. Substrate temperature is found to have a significant influence on the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the capacitors, while the influence of substrate pretreatment manifests itself in interface trap density, D_it, as measured by the Terman method.     

A simplified model for the static characteristics of amorphous silicon thin-film transistors

A simplified and more accurate expression for the static I_D − V_D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT) has been derived. The results show that the experimental drain characteristics agree very well with the derived equations. This model shows its greatest improvement over other models at low values of gate voltage and at large values of drain voltage. The model is based on the experimental function for the channel conductance vs gate voltage. Four constants, obtained from the experimental data of I_D vs V_G at some small value of V_D, are used to completely specify the simplified model. The theoretical results confirm the simple form of the model in terms of the device geometry. The constants calculated from the theory agree well with those extracted from the conductance data.     

The field effect electron mobility of laser-annealed polycrystalline silicon MOSFETs

Measured I_d-V_d results on MOSFET's and C–V results on MOS capacitors which were fabricated on laser annealed polycrystalline silicon are presented. A scanned CW Ar⁺ laser was used to anneal the samples. Laser power varied from 10 to 15 W in increments of 1 W; beam diameter was about 40 μ m and scan rate was about 12.5 cm/s. The field effect mobility, determined from I_d-V_d measurements, increases with increasing laser power. The effects of electron trapping in the polycrystalline silicon substrate were used to explain the observed mobility of the MOSFET's. In transistors annealed at low power (< 12 W), an intercrystalline potential barrier resulting from the electron trapping at crystallite and grain boundary regions was found to be the dominant factor in the channel electron conduction. Transistors annealed at high power (≥ 12 W) have fewer defect states and the intercrystalline barrier is dominant only in the low gate voltage region. In the high gate voltage region, surface structure imperfections, which cause scattering, limit the channel conduction.     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

Analysis of the quasi-saturation region of high voltage VDMOS devices

The effect of the epitaxial layer on the quasi-saturation region of the I_D(V_D) characteristic of a high voltage n-channel VDMOS structure is analysed. The proposed model takes into account the cylindrical shape of the P-well/N⁻-epilayer junction and the pinching effect of the current between neighbouring cells.     

Impact of bias condition on 1/f noise of dual-gate depletion type MOSFET in linear region and consequences for noise diagnostic application and modelling

This paper presents experimental and numerical results for 1/f noise of depletion-type dual-gate MOSFET (DGMOSFET) in the linear region of the output I_D-V_DS characteristics. In this region, both DGMOSFET inner transistors operate in either linear or non-linear region each. Gate-to-gate interelectrode spacing influence is taken into account in I_D-V_DS modelling with the effective parameter m_eff = μ_eff2L_eff1/μ_eff1L_eff2. For low bias conditions, the parameter m_eff can be reduced to the ratio of inner transistors channel effective lengths. A model for the normalized 1/f noise parameter and methodology for its calculation valid for the DGMOSFET linear region have been proposed. Due to interdependence of the inner transistors bias condition, their participation in total noise is controlled by weighting factors. This fact must be taken into account in the noise diagnostic procedure for DGMOSFET analysis.     

Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction

A new procedure is presented to separate the effects of source-and-drain series resistance and mobility degradation factor in the extraction of MOSFET model parameters. It requires only a single test device and it is based on fitting the I_D(V_GS, V_DS) equation to the measured characteristics. Two types of bidimensional fitting are explored: direct fitting to the drain current and indirect fitting to the measured source-to-drain resistance. The indirect fitting is shown to be advantageous in terms of fewer number of iterations needed and wider extent of initial guess values range.     

Deep depleted SOI MOSFETs with back potential control: A numerical simulation

We consider SOI MOSFET structures (N and P type) for which a control of the back potential of the epi layer is obtained by using a back gate. The effect of interface parameters on the back and front threshold voltages is analysed in case of a strong coupling between front and back interface (lightly doped epi layer).This analysis is carried out by a numerical integration of Poisson's equation throughout the structure. We thus obtain the potential profile, and the electron and hole densities, as a function of the applied front (V_g1 and back (V_g2) gate voltages. We also derive the I_d(V_g1, V_g2) characteristics in the case of l drain voltage.This program allows us to examine the dependence of both front and back threshold voltages on the interfacial parameters. It is also used to examine the validity of the existing analytical models and to interpret experimental results obtained on MOS/SOS transistors.     

Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device

The electrical properties of HfO₂ gate dielectric as a MOS structure deposited using Dense Plasma Focus (DPF) device under different ambient gases were investigated. DPF is unique machine used for the first time to fabricate a MOS device as it can be used to deposit dielectric film in one shot and can also be used to change the properties of the thin film surface. The films were first deposited under pre-optimized conditions of DPF device to have best focus for producing ions. The substrate for deposition of dielectric material was placed at a distance of 5 cm from the focus under argon ambient and then under nitrogen ambient. The I-V, C-V characteristics of the dielectric film were investigated employing Al-HfO₂-Si MOS capacitor structure deposited using DPF. The MOS devices were studied to determine electrical parameters like breakdown voltage, oxide charges and leakage current deposited under two different gas ambient. The microstructure of thin film is examined by using AFM and the thickness of the film is examined using an ellipsometer. The reduction in surface roughness, shift in Flat-band voltage (V_fb) and reduction in oxide-charge density (Q_ox) is seen maximum for MOS capacitor where HfO₂ as gate dielectric is deposited under nitrogen ambient using DPF machine.     

Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide

A method called strain-temperature stress was adopted in this work to improve the quality of ultra-thin oxide on both MOS(p) and MOS(n) capacitors. MOS structures were baked at 100 °C under externally applied mechanical stress. Reduced gate leakage current, reduced interface trap density (D_it), and improved time-dependent-dielectric-breakdown (TDDB) characteristics were observed after tensile-temperature stress treatment without increasing the oxide thickness. On the contrary, compressive-temperature stress resulted in a degraded performance of MOS capacitors. Consequently, the tensile-temperature stress method is suggested as a possible technique to enhance the ultra-thin oxide quality of MOS structure.     

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied Ω- and tri-gate structures to obtain abrupt switching (3–10 mV/decade) combined with a hysteresis in the I_D(V_DS) and I_D(V_GS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125 °C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the I_off. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.