Deep levels of platinum in silicon

Platinum has received renewed attention of late from device engineers as a means of lifetime-control in silicon. The energy levels assigned to platinum are not well defined, however, and ambiguities exist in the literature. In this work platinum was introduced into n- and p-type silicon and the energy levels and concentrations studied by thermally stimulated current and capacitance techniques. p]Schottky barrier diodes were used to study electron emission from two levels found in the upper half of the band gap. The use of Schottky barriers eliminated the problem of process-induced defect introduced by high concentration p⁺ diffusions. Phosphorus-diffused n⁺ - p diodes were used to study hole emission from three levels found in the lower half of the band gap. Platinum concentration versus distance profiles were obtained from thermally stimulated capacitance measurements. Experimental results indicate that the platinum concentration follows the boron concentration distribution near the junction in p-type silicon.     

Energy levels and degeneracy ratios for chromium in silicon

The energy levels and the degeneracy ratios for chromium in silicon have been determined by the Hall coefficients which were measured by the van der Pauw method. Using the curve fitting method for carrier concentration based on the charge balance equation with the root mean square deviation, the analysis shows that chromium in silicon gives rise to two donor levels. The energy levels of the upper and lower donors are located at E_c-0.226(±0.010)eV and E_v+0.128(±0.005)eV, and their degeneracy ratios are 1/3 and 1/4, respectivel     

Energy levels and degeneracy ratios for magnesium in n-type silicon

The energy levels and degeneracy ratios of magnesium in n-type silicon have been determined by Hall effect measurements with the least square method. Magnesium ions appear to occupy two different sites and show different electrical properties. The first is amphoteric and exhibits an acceptor level at E_c ? 0.115 eV (±0.002 eV), degeneracy ratio γ_I^? = 2.5 as well as a donor level at E_c ? 0.40 eV (±0.01 eV), γ_III⁺ = 1. The second exhibits a donor level at E_c ? 0.227 eV (±0.004 eV), degeneracy ratio $\text{γ}{}_{\mathrm{II}}{}^{\mathrm{+}}\text{=}\text{1}\text{2.5}$. The physical nature of these Mg associated site is unknown.     

Energy levels of vacancies and interstitial atoms in the band gap of silicon

Based on the analysis of the secondary processes of radiation-induced defect formation in Si crystals with charge-dependent selective traps for vacancies and interstitial atoms, the energy levels of vacancies and interstitial atoms were identified; these level were determined previously from the effect of the irradiation conditions on the annihilation rate of elementary primary defects. It is ascertained that the levels at ～E _c -0.28 eV and at ～E _c -0.65 eV in the band gap of Si belong, most likely, to vacancies; the levels at ～E _c -0.44 eV, at ～E _c -0.86 eV, and, presumably, at ～E _c -0.67 eV belong to intrinsic interstitial atoms.     

Photoionization cross-sections and energy levels of gold,iron, platinum,silver, and titanium in silicon

The photoionization cross-sections of various deep impurities of interest in solar-grade silicon for photovoltaic cells, and the corresponding energy levels, have been determined by steady state photo-induced currents in pn junctions or Schottky barrier junctions irradiated simultaneously with two wavelengths of light. Light of about half the band-gap energy controls the occupancy of the deep impurity level and the spectral dependence of the photocurrent on a higher photon energy light source then provides, via the Lucovsky model, the photo-cross-section and the impurity energy level. The results obtained for Au and Pt in Si are in agreement with those of Braun and Grimmeiss and the energy levels for Fe, Ti, and Ag obtained optically are in agreement with those obtained by other methods.     

Trapping levels in silicon nitride

The trapping levels in silicon nitride have been investigated using the thermally stimulated current technique. Traps at between 0.50 and 0.90eV below the conduction band of the nitride were found, as well as a distribution of traps at and near the silicon-silicon nitride interface about 0.10eV below the conduction band of the silicon.     

Defect levels in chromium-doped silicon

The transient capacitance technique has been used to study the chromium-related levels in the silicon band gap. Chromium was diffused at temperature of 1100 and 1150°C for 0.5 and 3 hr. Five different levels at E_c?0.11 eV, E_c?0.21 eV, E_c?0.28 eV, E_c?0.36 eV and E_c?0.45 eV were obtained from the Arrheniu plots of the electron thermal-emission rates. The number of levels in the upper half of the band gap decreased from five to two with an increase of Cr-diffusion period. Two levels were located at E_c?0.20 eV (donor) and E_c?0.43 eV (acceptor). A donor level was also observed at E_v + 0.25 eV. The donor level was not affected by the diffusion condition. The majority carrier capture cross sections of the three dominant levels have been measured by the transient capacitance technique modified by the pulse transformer. The values were σ_n = 4.1 × 10^?15 cm² for the upper donor at E_c?0.20 eV, σ_n = 2.0 × 10^?16 cm² for the acceptor at E_c ?0.43 eV and σ_p = 9.1 × 10^?18 cm² for the lower donor at E_v + 0.25 eV, and were independent of temperature. The three dominant levels are due to distinct chromium centers.     

Copper impurity levels in silicon

This paper presents a new model of copper impurity levels in silicon, and suggests a new method to analyze the parameters of multilevel impurities using Hall data. On the assumption that the energy levels of copper do not depend on the conduction type of silicon and the concentration of copper, an impurity level model which can explain all the Hall data of many different copper-doped silicon samples is proposed using a computer-aided numerical analysis. Experimental data and analysis indicate that copper exists in silicon in the form of four independent species, viz. substitutional species (Cu_I), interstitial species (Cu_IV) and two copper-associated species Cu^II and Cu^III. The usual species Cu^I has three acceptor levels and a donor level below the intrinsic level. Cu^II has two levels, an acceptor and a donor level respectively, below the donor level of Cu^I. Cu^III produces an acceptor level at a slightly distant position from the conduction band edge. That the intersitial species Cu^IV behaves as a shallow donor is well-known, but its behavior is predominant only in samples diffused at temperatures below 900°C because of the precipitation of its species. Not only the energy levels of copper, but also the degeneracy ratios associated with these levels have been simultaneously determined, and it has been indicated that the degeneracy ratios have an important effect on the temperature dependence of the carrier concentration.     

Effects of Si interlayer conditions on platinum ohmic contacts for p-type silicon carbide

A study of Pt ohmic contacts with Si interlayers on p-type SiC (7.0×10¹⁸ cm⁻³) was performed as a function of the Si interlayer thickness, deposition temperature, and dopant incorporation. All contacts were ohmic after annealing at 1100°C for 5 min in vacuum. The use of a Si layer was found to decrease the specific contact resistance (SCR) relative to Pt contacts that did not contain Si, regardless of the deposition conditions used in this study. The SCR values were reduced further by three independent effects: the deposition of the Si layer at 500°C, the incorporation of B in the layer, and the design of the Pt:Si layer thicknesses in a 1:1 atomic ratio. By combining all of these effects, the lowest average SCR values (2.89×10⁻⁴ Ω cm²) were obtained. After annealing for 5 min at 1100°C, x-ray diffraction of the contacts with the 1:1 Pt:Si ratio showed a single phase of PtSi. Analyses by cross-sectional transmission electron microscopy revealed no reaction of the films with the SiC substrate. The electrical characteristics of these contacts were stable after annealing at 400°C and 600°C for 96 h and 60 h, respectively. These results are in contrast to those observed for pure Pt contacts and for contacts containing a higher Pt:Si ratio.     

The properties of aluminum, platinum silicide and copper based contacts for silicon high-power devices

Electrical, thermo-electrical and thermo-mechanical properties were compared for PtSi, aluminum (Al, PtSi-Al, PtSi-AlCuSi, PtSi-TiW-AlCuSi), and copper based contacts (TiW-Ni-Cu, TiW-Ni-Cu-Ni-Au, PtSi-TiW-Ni-Cu, PtSi-TiW-Ni-Cu-Ni-Au). High-power 2.5 kV/150 A P-i-N diode with both lapped and etched anode surface was used to characterize the performance of the contacts in the conditions of free floating silicon in pressed package. The devices with PtSi contacts have the lowest forward voltage drop, but do not survive the operation in pressed package under thermal cycling. The copper based contacts with PtSi layer give lower voltage drop and better thermo-mechanical ruggedness compared to that of aluminum. These features are conserved even with passivation against corrosion using Ni-Au. The contacts without the PtSi layer have high voltage drop and fail under thermal cycling. The composition of the contact layer is shown to influence the thermal behavior of device voltage drop. The crossing point current is found to decrease with increasing contact layer thickness. The lowest magnitude gives the aluminum contact.     

DEEP LEVELS RELATED TO COPPER IN SILICON

Energy positions and carrier capture cross sections of the deep levels related to copper insilicon are measured by the DLTS.The annealing behaviour and spatial distributions of some of these levelsare also studied.The results show that there are no triple aceeptor or quadruple states corresponding to thesubstitutional copper in silicon,which have been reported in literature.Most of the deep levels related tocopper in silicon correspond to complexes of copper and defects in silicon.     

The energy levels of palladium in silicon

A study is undertaken of the energy levels of palladium in silicon. It is shown that electronically active palladium exists in silicon in the form of two independent species. The first, designated Pd_I, is amphoteric and exhibits an acceptor level at 0.22±0.01 eV below the conduction band edge, as well as a donor level at 0.33±0.01 eV above the valence band edge. The second species, designated Pd_II, exhibits an acceptor level at 0.32±0.1 eV above the valence band edge. The ratio of Pd_I to Pd_II which is incorporated into the silicon varies from 40 to 5 for diffusion temperatures from 900 to 1200°C respectively.     

Calculation of 2p levels for thermal double donors in silicon

A two-center model is developed to explain the electronic structure of thermal double donors (TDD) in silicon. Calculations of 2p levels of singly ionized TDD’s are performed in the effective mass approximation. From a comparison of the calculated results with the experimental data, the internuclear distance between the two electrically active atoms is evaluated as 0.75–0.95 nm for the TDD1–TDD3 and 1.35–1.75 nm for the next four species: TDD4–TDD7. Fiz. Tekh. Poluprovodn. 31, 961–965 (August 1997)     

Resistivity and deep impurity levels in silicon at 300 K

Families of curves of the resistivity at 300 K for n- and p-type silicon doped with deep activation energy impurities are presented as a function of impurity concentration. These curves are based on analyses of Irvin's curves, applicable to the shallow activation energy impurities, and on the properties of the deeper activation energy impurities. These curves apply to impurities with activation energies that are independent of concentration. Since Irvin's p-type curve appears to be heavily influenced by Si:Ga data in the 10¹⁶-10¹⁸-cm^-3range, a boron curve is calculated for this range. This curve may be considered a correction to Irvin's p-curve in this impurity range.     

Energy efficient computation: A silicon perspective

Building and deploying an energy-efficient infrastructure for computation requires coordination across a large number of disciplines, from the end-user application software to the device that performs the actual computation through layers of virtualization software, operating systems, communication networks, data center architectures, arrays of servers, and others. While the most optimal savings can be achieved by careful coordination among all of the elements, there are opportunities for improvement on each individual component of the system. In particular, at the very core of computation, the processing elements are silicon devices embedded in integrated circuits. In this paper, an overview of the state of the art in building efficient silicon for computational applications is presented, including the techniques actively used by the industry, the upcoming new technologies, and the research initiatives geared toward the future.     

Energy distribution of localized states in amorphous hydrogenated silicon

A new method for determining the spectral dependence of the optical-absorption coefficient in amorphous hydrogenated silicon is suggested. The method is based on the analysis of spectral and temperature dependences of transient photoconductivity in this material. Energy distribution of localized states involved in recombination of nonequilibrium holes was calculated.     

Autosolitons in bistable system of silicon with deep impurity levels

Autosolitons in the bistable system of silicon associated with the thermal and electric-field ionization of In deep acceptor levels at a temperature of 77 K are experimentally found and investigated. It is shown that the positive feedback on the activator is related in the considered model of autosolitons to an increasing dependence of the lattice temperature on growth in the hole concentration, while the damping role of the inhibitor is associated with a decrease in the charge-carrier temperature during phonon-induced scattering. This leads to power-loss reduction and lattice-temperature restriction in the vicinity of autosolitons.     

A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.     

Interstitial iron concentrations across multicrystalline silicon wafers via photoluminescence imaging

We present high‐resolution images of the lateral distribution of interstitial iron across wafers from various positions along the length of a directionally solidified multicrystalline silicon ingot. Iron images were taken on wafers in the as‐cut state and also after two different phosphorus gettering steps performed at 845°C for 30 min, one with an additional anneal at 600°C for 5 h (referred to as extended gettering). The iron images were obtained by taking calibrated photoluminescence (PL) images of the low injection carrier lifetimes, before and after dissociation of iron–boron pairs via strong illumination. The iron images clearly reveal the internal gettering of iron during ingot cooling to grain boundaries and dislocation clusters, resulting in much lower dissolved iron concentrations at those features. In contrast, the PL images of gettered wafers exhibit a reversed distribution of dissolved iron compared to the as‐cut wafers, in other words, with higher interstitial iron concentrations at the grain boundaries than within the grains, most probably owing to the precipitated iron at the grain boundaries partly dissolving during the high‐temperature gettering process. Phosphorus gettering was found to result in a significant reduction of interstitial iron both inside the grains and at grain boundaries. The extended gettering resulted in a further significant reduction in all parts of the wafers and along all sections of the ingot. Copyright © 2011 John Wiley & Sons, Ltd.