Non-equilibrium ψs vs Vg characteristics of MOS capacitors and related effects

A new method for measuring the non-equilibrium surface potential of an MOS capacitor as a function of gate voltage is described. The system response is related to the bulk trap generation rate, and the technique is then used for finding generation rate at various surface potentials and, hence, depletion widths. Using this value of generation rate in the theoretical ψ_s vs V_g equation, results in curves that are in excellent agreement with the experimental results. The generation rate is then used to obtain the theoretical IV characteristics of the capacitor subjected to a constant voltage ramp. These characteristics are also found to be in excellent agreement with corresponding experimental characteristics. Finally, the observed anomalous behaviour of the quasi-static section of the reverse sweep curve of the ψ_s vs V_g plots is explained using a p-n junction analogy.     

A study of diffused bipolar transistors by electron microscopy

Shallow junction bipolar transistors have been fabricated on bulk (001) silicon starting material using a diffusion processing technology. The resultant junction depths were about 0.5 and 0.8 μ m respectively for the emitter-base and base-collector junctions. The crystallographic defects present have been detected and characterized using a combination of electrical measurements, the electron beam induced current (EBIC) mode of the scanning electron microscope (SEM) and both conventional and high voltage transmission electron microscopy (TEM).Two types of dislocations were identified in the TEM. The first consisted of an orthogonal array of sessile, diffusion-induced edge dislocations located about halfway down in the heavily doped emitter. The second type consisted of 60° glissile dislocations that looped down from the orthogonal array and in some cases penetrated the emitter-base junction.Observations of a number of 60° dislocations yielded a good correlation between their depth and their contrast when imaged in the EBIC mode of the SEM. The 60° dislocations locally retard the emitter diffusion when they lie near to the emitter-base junction. Local breakdown effects under reverse bias were observed at the sites of these dislocations.     

Proper choice of the measuring frequency for determining fT of bipolar transistors

The permissible frequencies (f) for measuring f_T are restricted to a certain range characterized by the condition $\text{f}{}_{\mathrm{T}}\text{= /s|β/s| f =}\text{const., i.e.}\text{/s|β/st| }}\text{1}\text{f}$. The boundaries of this range are determined by an analytical calculation and confirmed both by measurements and accurate computer simulations. It is shown that the upper measuring frequency limit f_h of high-speed transistors may drastically be reduced due to the strong influence of parasitic transistor and package parameters (e.g. f_h = 0,1 … 0,2f_Tmax. Therefore the operator must carefully choose his measuring frequency, by use of the relations presented, in order to avoid large errors in determining f_T and the other important transistor parameters (τ_n,C_eb) which can be derived from the current dependence of f_T.     

Determination of surface state density from gm − VG characteristics of MOSFETs

The g_m - V_g characteristics of a MOSFET measured at the room temperature in the transition region between the normal and the low level current regions are compared with the theoretical curve to obtain the surface state density, ρ_SS, within a small surface potential interval near the threshold voltage. It is further shown theoretically that the peak value of g_m, g_m0, reduces against the increase of ρ_SS by the factor 1/(1 + αρ_SS) where α is a constant, and good agreement is obtained between theory and experiment by using the devices in which surface states are produced by the RF sputter coating with SiO₂. The gate voltage corresponding to $\text{g}{}_{\mathrm{m0}}\text{or}\text{g}{}_{\mathrm{m0}}\text{10}$ is shown to be linearly dependent on ρ_SS, but the gate voltage shift is considerably small at the lower current level, indicating the surface state density increasing sharply towards the valence band edge.     

Extrapolated fmax of heterojunction bipolar transistors

It is shown that the extrapolated f_max of heterojunction bipolar transistors (HBT's) can be written in the form f _max=√f_T/8π(RC)_eff, where f_T is the common-emitter, unity-current-gain frequency, and where (RC)_eff is a general time constant that includes not only the effects of the base resistance and collector-base junction capacitance, but also the effects of the parasitic emitter and collector resistances, and the dynamic resistance 1/g_m, where g_m is the transconductance. Simple expressions are derived for (RC) _eff, and these are applied to two state-of-the-art devices recently reported in the literature. It is demonstrated that, in modern HBT's, (RC)_eff can differ significantly from the effective base-resistance-collector-capacitance product conventionally assumed to determine f_max     

Early voltage in double heterojunction bipolar transistors

The Early voltage for abrupt double heterojunction bipolar transistors (DHBTs) has been calculated by using an effective junction velocity (S_c) at the base-collector heterojunction. S_c is obtained by self-consistently partitioning thermionic and quantum mechanical tunneling currents. Unlike single heterojunction bipolar transistors (SHBTs), the Early voltage varies very rapidly at low reverse bias and approaches the SHBT-limit at sufficiently high reverse bias. This is attributed to the presence of an energy barrier at the b-c heterojunction     

The temperature dependence of ideal gain in double diffused silicon transistors

Theoretical treatments predict higher injection efficiency for double diffused silicon transistors than the experimentally observed values. This paper shows that the discrepancy can be partly explained by the difference in the effective energy gaps in the emitter and base regions. Coulomb interaction of the free carriers results in lower energy gap in the heavily doped emitter than in the rest of the transistor. The difference in the energy gaps is experimentally determined from the activation energy difference of the emitter-current and the ideal component of the base Current. It is concluded that too much doping in the emitter lowers the transistor gain, increases the temperature dependence of the gain, and results in a higher excess noise.     

InP/InGaAs double heterostructure bipolar transistors grown by MBE

Double heterostructure bipolar transistors have been fabricated on InP/InGaAs MBE material. Current gains of up to 80 have been observed in the emitter-up configuration. The devices were fabricated using two diffusion techniques and selective etching to contact the base.     

Mobility models for the I–V characteristics of buried-channel MOSFETs

This paper presents two separate carrier-mobility models for the I-V characteristics of buried-channel MOSFETs. One model considers oxide-semiconductor interface scattering for carrier motion in the surface accumulation layer; the other model considers the scattering of carrier motion within the finite thickness of the neutral buried channel. Based on these two carrier-mobility models, the I-V characteristic model of buried-channel MOSFETs is derived analytically without considering the small-geometry effects. Comparisons between the developed I-V characteristic model and the experimental results of the fabricated buried-channel MOSFETs have been made. It has been shown that the mobility models developed enable us to accurately simulate the I-V characteristics of buried-channel MOSFETs operated over wide ranges of gate-source and back-gate biases.     

High breakdown voltage InGaAs/InP double heterojunction bipolar transistors with fmax=256 GHz and BVCEO= 8.3 V

正An InGaAs/InP DHBT with an InGaAsP composite collector is designed and fabricated using triple mesa structural and planarization technology.All processes are on 3-inch wafers.The DHBT with an emitter area of 1 x 15μm~2 exhibits a current cutoff frequency f_t = 170 GHz and a maximum oscillation frequency f_(max) = 256 GHz.The breakdown voltage is 8.3 V,which is to our knowledge the highest BV_(CEO) ever reported for InGaAs/InP DHBTs in China with comparable high frequency performances.The high speed InGaAs/InP DHBTs with high breakdown voltage are promising for voltage-controlled oscillator and mixer applications at W band or even higher frequencies.     

高击穿电压的InGaAs/InP双异质结双极型晶体管

利用台面工艺以及平坦化技术制作了带有复合式集电区的InGaAs/InP双异质结双极型晶体管。所有的工艺都是在3英寸圆片上进行的。发射极面积为1μm15μm的器件,电流增益截止频率为170GHz,最高振荡频率为256GHz,击穿电压为8.3V,这是国内报道的击穿电压最高的InP HBT器件。高的振荡频率以及击穿电压,使得此种类型的器件十分适用于W波段及以上频段压控振荡器（VCO）以及混频器（Mixer）的制作。     

High frequency breakdown in diffused transistors

In addition to offering such desirable performance characteristics as very large bandwidth and appreciably high current gain, transistors manufactured by diffusion techniques possess a high frequency voltage capability that is significantly in excess of the breakdown voltage which materializes under quiescent operating conditions. This paper attributes voltage capability enhancement in diffused transistors to the excess phase which is evidenced in the current gain characteristics of these devices. An "excess breakdown function," developed in this paper, permits direct calculation of the factor by which quiescent breakdown specifications can be safely exceeded at given frequencies of operation.     

A computer-aided design model for high-voltage double diffused MOS (DMOS) transistors

High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel, and of spreading resistance in the drift region are considered. Parameter extraction for experimentally characterizing these effects is described. Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics. The range of validity of the model is limited primarily by high current saturation effects.     

Mosfet devices with trapezoidal gates: I–V characteristics and magnetic sensitivity

MOSFET transistors may be fabricated with a variety of channel geometries. The trapezoidal shape for the gate provides useful I–V characteristics. Channel probes are diffused for sensing Hall voltages developed across the device channel. This paper matches experimental and theoretical results for trapezoidal-gate, p-channel, enhancement-mode MOSFET devices. A nonparabolic variation of drain current with gate bias is observed. An optimum gate bias for maximum magnetic sensitivity is obtained for MAGFETs.Devices are fabricated with substrates oriented along the (100) and (111) crystallographic planes. A mobility variation with gage bias is required to accurately match the experimental measurements.     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

A V-groove oxide isolated bipolar bucket brigade shift register

A V-groove oxide isolated bipolar bucket brigade shift register structure is described in this paper. The operation of the shift register is analyzed to determine the frequency and transfer efficiency limitation and point out the inherent advantages of such a structure. Measurements carried out on experimental 36-stage V-groove BBD registers are presented to demonstrate the capabilities of the devices. The proposed V-groove BBD structure results in registers with higher operating frequencies and greatly increased packing density when compared to standard junction isolated devices. These improvements are obtained without sacrificing the low or mid-frequency response and make these devices useful in video delay line applications.