Optimization of Material and Process for Fine Pitch LVSoP Technology

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low‐volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μm, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine‐pitch interconnection of a Cu pillar in the semiconductor packaging field.     

Multiwavelength light emitters for scanning applications fabricatedby flipchip bonding

We present a multiwavelength light source which was fabricated using a self-aligned flipchip bonding technique. The device consists of an InGaN-GaN light-emitting diode emitting light at around 420 nm, on top of which we flipchip-bonded a monolithically integrated red/infrared dual-beam laser. The upper two lasers were built by selective removal of the red laser, and subsequent regrowth of an infrared laser structure. Since all processes, including the deposition of the PbSn solder bumps for bonding, were based on photolithographic precision, tight alignment tolerances of ±μm in the lateral direction could be fulfilled between the ridge waveguides of the three light emitters. For a high-speed color scanning system, this is an important design criterion because it will allow the use of a single scanning optics for the three laser beams     

Fine‐Pitch Solder on Pad Process for Microbump Interconnection

A cost‐effective and simple solder on pad (SoP) process is proposed for a fine‐pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60‐μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine‐pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine‐pitch SoP process and evaluate the fine‐pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45‐μm diameter and 60‐μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine‐pitch SoP and microbump interconnection using a screen printing process.     

Connection of VLSI chips to printed circuit board using stacked solder bumps

A new type of flip-chip interconnection technology usingstacked solder bumps is proposed, where the diameter of theupper solder bump is less than that of the lower ones. This isto reduce the capacitance between the stacked solder bumps and the ground plane and to prolong the lifetime ofthe solder joints.     

Electroless remetallization of aluminum bond pads on CMOS driverchip for flip-chip attachment to vertical cavity surface emitting lasers(VCSEL's)

A method for remetallizing the bond pads of electronic chips, which are initially metallized with aluminum or aluminum alloy is presented. Application of electroless plating process for the remetallization of aluminum to a solderable gold surface can reduce the cost and complication of the widely accepted flip-chip interconnection technology. We have developed a step by step nickel/gold wafer bumping technique (remetallized bump height is 5.0 μm) for the appropriate solder (15.0 μm of In:Pb). Variation of roughness of the remetallized surface has been studied carefully. We have completed prototype research studies on test devices and successfully packaged the flip-chip bonded hybrid pair of a CMOS driver chip and a dummy structure of vertical cavity surface emitting laser (VCSEL) array. Cross section of the flip-chip solder joint is studied. Also, adhesion strength of the metal deposit is investigated     

Laser-assisted bumping for flip chip assembly

A novel laser-assisted chip bumping technique is presented in which bumps are fabricated on a carrier and subsequently transferred onto silicon chips by a laser-driven release process. Copper bumps with gold bonding layers and intermediate nickel barriers are fabricated on quartz wafers with pre-deposited polyimide layers, using UV lithography and electroplating. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using light incident through the carrier. Bumps of 60 to 85 μm diameter and 50 μm height at a pitch of 127 μm have been fabricated in peripheral arrays. Parallel bonding and subsequent transfer of arrays of 28 bumps onto test chips have been successfully demonstrated. Individual bump shear tests have been performed on a sample of 13 test chips, showing an average bond strength of 26 gf per bump     

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 ± 3.5 μm, and a maximum-to-minimum bump height range of 17 μm over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 μm peripheral pitch. A 109.6 ± 1.3 μm bump height on orthogonal array with 250 μm pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 × reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +125°C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121°C, 100% RH, 15 psig test condition     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 μm by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than ±0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260°C in N₂ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150°C for 1000 h in N₂ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs     

A new flip-chip bonding technique using micromachined conductivepolymer bumps

Using micromachining techniques with thick photoresists, a new conductive polymer flip-chip bonding technique that achieves both a low processing temperature and a high bumping alignment resolution has been developed in this work. By the use of UV-based photolithography with thick photoresists, molds for the flip-chip bumps have been patterned, filled with conductive polymers, and then removed, leaving molded conductive polymer bumps. After flip-chip bonding with the bumps, the contact resistances measured for 25 μm-high bumps with 300 μm×300 μm area and 400 μm×400 μm area were 35 mΩ and 12 mΩ respectively. The conductive polymer flip-chip bonding technique developed in this work shows a very low contact resistance, simple processing steps, a high bumping alignment resolution (<±5 μm), and a lower bonding temperature (~170°C). This new bonding technique has high potential to replace conventional flip-chip bonding technique for sensor and actuator systems, bio/chemical μ-TAS, optical MEMS, OE-MCM's, and electronic system applications     

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Hybrid integration of surface-emitting microlaser chip and planaroptics substrate for interconnection applications

The bonding of a monolithic array of surface-emitting microlasers onto a glass substrate that contains a matching array of microlenses and mirrors is reported. The bonding was achieved by flip-chip solder bump bonding using indium as the solder material. The alignment precision is within ±2 μm. The optical substrate provides a simple interconnection scheme that routes the light from each laser to well defined output positions     

Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies

Flip-chip technology is increasingly prevalent in electronics assembly [three-dimensional (3D) system-in-package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The obtained constitutive law of the HEM was then implemented in finite-element software (Abaqus^®). Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization–localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely the stress and strain fields in these phases, two models of structural zoom, taking into account the real solder bump geometry, have been tested. The obtained local stress and strain fields corroborate the experimentally observed damage initiation of the solder bumps.     

Compact packaging of optical and electronic components for on-board optical interconnects

An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45/spl deg/ mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links.     

Manufacturing and materials properties of Ti/Cu/ElectrolessNi/solder bump on Si

This work attempted to fabricate the solder bump with the structure: Si/Ti/Cu/Electroless Ni/solder. The shear strength of the solder bump, with bump pad of 60 μm in diameter, is around 15 g/bump prior to and after reflow. The solder bumps fractured at the solder. Humidity test at 85% of relative humidity at 85°C and a high temperature treatment at 150°C for 1000 h tend to downgrade the shear strength of the solder portion of the bump, yet not the interface. Both treatments enhance the growth of intermetallic compound (IMC) formed between Ni and solder. The barrier effect of electroless nickel deposit was investigated     

化学镀镍、模版印刷法制备倒扣芯片焊料凸点

回顾了低成本制备芯片上焊料凸点的方法,即化学镀镍制备凸点下金属层、模版印刷焊料,最后回流形成焊料凸点,并综述了该方法的最新研究进展.     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated.      

Reflow and property of Al/Cu/electroless nickel/Sn-Pb solder bumps

Materials interaction, shearing strength, and bump growth of Al/Cu/electroless nickel/Sn-Pb solder bumps were investigated with respect to reflow conditions. Shearing strength of the solder bump is as high as 64 g/bump for a bump pad dimension of 100×100 μm. Reflow temperature enhances the shearing strength while repeating reflow downgrades the shearing strength to a lowest value of 35 g/bump. A greater bump height is achieved when reflow was conducted at a slower heating rate. Cu penetrates the electroless nickel (EN) layer after reflow, while Al remains unmoved. The diffusion behavior of Cu through the EN layer is discussed. Ni-Sn and Cu-Sn intermetallic compounds form during reflow