High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Anodic oxide film as gate insulator for InP MOSFETs

An anodic oxide film of InP, which had an interface state density of ? 1011 cm?2 eV?1 near midgap and worked well as the gate insulator for InP MOSFETs, was obtained by optimising its preparation conditions. The excellence of the anodic oxide as a gate insulator was confirmed by a high electron effective mobility (1500 cm2/Vs) in the accumulation-mode InP MOSFETs.     

High temperature SiC trench gate p-IGBTs

Various design issues pertaining to SiC-based IGBTs are described. A trench gate, p-channel IGBT was considered the most appropriate structure for fabrication in SiC. The fabrication and characterization of high temperature SiC IGBTs with high current levels are presented. Using optimized emitter processing, 6H-SiC p-IGBTs show a higher current capability than 4H-SiC p-IGBTs because of their lower emitter contact resistance and higher MOS channel mobility. Since IGBTs rely on minority carrier injection, the low bulk mobility parallel to the c-axis in 6H-SiC was not found to severely affect the current carrying capability as compared with 4H-SiC IGBTs in the present design. Measured results of these devices are described from room temperature to the 350-400/spl deg/C temperature range. For both polytypes, the current capability was found to be much larger when their MOS gates were fabricated in the 112~0 crystal direction compared with the 1100 crystal direction. The emitter (p-type) contact anneal was also found to significantly affect the performance of SiC IGBTs. 4H-SiC IGBTs showed a -85 V blocking capability (room temperature) and on-current of 100 mA at 350/spl deg/C. 6H-SiC IGBTs were demonstrated with -400 V blocking capability (at 25/spl deg/C) and 2 A at 400/spl deg/C.     

InGaAs enhancement-mode MISFETs using double-layer gate insulator

In this letter we describe the fabrication of enhancement-mode MISFETs on InGaAs grown by liquid-phase epitaxy (LPE) using an anodic Al2O3/anodic native oxide double layer as a gate insulator. The normally-off device of 10 ?m gate length shows the effective channel mobility of 1400 cm2/Vs. The interface state density distribution of this double-layer MIS of InGaAs is also reported. The density of 2 × 1013 cm?2 eV?1 at Ec ?0.057 eV and the minimum of 8 × 1011 cm?2 eV?1 near midgap are measured from C/V characteristics.     

Low-voltage organic thin film transistors with hydrophobic aluminum nitride film as gate insulator

This paper reports on the low-voltage (<5 V) pentacene-based organic thin film transistors (OTFTs) with a hydrophobic aluminum nitride (AlN) gate-dielectric. In this work, a thin (about 50 nm), smooth (roughness about 0.18 nm) and low-leakage AlN gate dielectric is obtained and characterized. The AlN film is hydrophobic and the surface free energy is similar to the organic or the polymer films. The demonstrated AlN–OTFTs were operated at a low-voltage (3–5 V). A low-threshold voltage (−2 V) and an extremely low-subthreshold swing (∼170 mV/dec) were also obtained. Under low-voltage operating conditions, the on/off current ratio exceeded 10⁶, and the field effect mobility was mobility was 1.67 cm²/V s.     

Highly reliable ultrathin silicon oxide film formation at lowtemperature by oxygen radical generated in high-density krypton plasma

This paper focuses attention on electrical properties of silicon oxide films grown by oxygen radical generated in Kr/O₂ mixed high-density microwave-excited plasma at 400°C. They represent high growth rate, low activation energy, high dielectric strength, high charge-to-breakdown, and low interface trap density and bulk charge enough to replace thermally grown silicon oxide     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Inversion-mode InP MISFET using a photochemical phosphorus nitride gate insulator

An inversion-mode n-channel InP MISFET is fabricated using a photochemical phosphorus nitride film as a gate insulator. An effective electron mobility of ~1700 to 2200 cm2/Vs is obtained and the drain current maintains more than 80% of its initial value after 103 s at room temperature. These values are much superior to the characteristics of InP MISFETs using thermally deposited phosphorus nitride gate insulators. These improvements are probably caused by the reduction of thermal degradation of InP substrates through the application of the photochemical CVD technique.     

InP high mobility enhancement MISFETs using anodically grown double-layer gate insulator

High-mobility InP enhancement MISFETs are fabricated with the use of a novel double-layer gate insulator consisting of Al2O3 and native oxide, both grown anodically by a simple process. Applying a fairly high-temperature annealing (400°C), channel mobilities of 1500?3000 cm2/Vs and a large reduction of drain current drift are achieved.     

High-speed integrated circuits based on InP-MISFETs with plasma SiO2 gate insulator

High-speed, direct-coupled FET logic and inverter integrated circuits were fabricated with InP-MISFETs incorporating, for the first time, a plasma-SiO₂ gate insulator. These circuits employed 3-μm gate-length MISFET drivers and MESFETs as the load. The MISFET drivers showed channel mobilities in the range of 2100 cm² V^?1 sec^?1 and negligible current drift up to 10⁴ sec. The DCFL circuit, with a power supply voltage of 4 V, showed a typical propagation delay per stage of 80 pS with an associated power-delay product of 57 fJ. For inverters, a logic swing of 3.38 V, a d.c. gain of 1.9 in the linear region and noise margins of 0.92 and 0.80 V were observed.     

Improved sensing characteristics of MISiC Schottky-diode hydrogen sensor by using HfO2 as gate insulator

Hafnium dioxide deposited by RF sputtering is used as the gate insulator of metal–insulator–silicon–carbide (MISiC) Schottky-diode hydrogen sensors. Sensors with different gate insulator thicknesses are fabricated for investigation. Their hydrogen-sensing properties are compared with each other by taking measurements at various temperatures and hydrogen concentrations using a computer-controlled measurement system. Experimental results show that for the same insulator thickness, the HfO₂ sensor is more sensitive than its SiO₂ counterpart. This should be mainly attributed to the larger barrier-height at the Pt/HfO₂ interface which can reduce the current of the sensor before hydrogen exposure. Moreover, the sensitivity initially increases with the thickness of the HfO₂ film because a thicker oxide layer can provide a larger barrier-height reduction upon hydrogen exposure. However, further increasing the thickness of the HfO₂ dielectric beyond about 3.3 nm reduces the sensitivity, possibly due to more trapped charges in thicker high-k dielectric which can screen the effect of the polarized hydrogen layer.     

Organic–inorganic hybrid materials as solution processible gate insulator for organic thin film transistors

We synthesized organic–inorganic hybrid materials (hybrimers) using a simple non-hydrolytic sol–gel reaction and applied the materials as gate insulators in organic thin film transistors (OTFTs). The hybrimer thin films had smooth and hydrophobic surfaces, and were stable with solvents. In addition, the hybrimer thin films had good electrical properties such as low leakage current and high dielectric strength. The performance of the OTFT with hybrimer gate insulator fabricated by drop casting of regioregular poly(3-hexylthiophene) (P3HT) was similar to that of OTFT with hexamethyldisilazane (HMDS) treated thermally grown SiO₂. The hysteresis of RR-P3HT based OTFT with hybrimer gate insulator was negligible.     

Residual damage effects on gate contacts formed on SiC surfaces etched by using the amorphization technique

A trench fabrication process has been proposed and experimentally demonstrated for silicon carbide using the amorphization technique. In the present work, the quality of gates [oxide for metal oxide semiconductor field-effect transistors (MOSFETs) and Schottky barrier contacts for metal semicondcutor field-effect transistors (MESFETs)] fabricated on the etched surfaces are compared with those formed on the as-grown silicon carbide surface. The resistivity and breakdown electric field of the thermal oxide grown on the etched surface was found to be comparable to that of thermal oxide grown on silicon. However, a large concentration of acceptor type interface states (0.5-1 x 10¹³ cm⁻²eV⁻¹) was observed. This results in a large negative interface charge at room temperature and a significant shift in flat band voltage as a function of temperature, which makes the process unsuitable for formation of gates in UMOSFETs. Titanium Schottky contacts formed on the etched surface showed superior reverse current-voltage characteristics and higher breakdown voltages than the Schottky diodes formed on unetched surface with similar doping concentrations. This indicates that the argon implant process for trench formation is suitable for fabrication of gate regions in high voltage vertical MESFETs (or SITs).     

Low voltage copper phthalocyanine organic thin film transistors with a polymer layer as the gate insulator

Low voltage organic thin film transistors(OTFTs) were created using polymethyl-methacrylate-co g-lyciclyl-methacrylate(PMMA-GMA) as the gate dielectric.The OTFTs performed acceptably at supply voltages of about 10 V.From a densely packed copolymer brush,a leakage current as low as 2×10~(-8) A/cm~2 was obtained.From the measured capacitance-insulator frequency characteristics,a dielectric constant in the range 3.9-5.0 was obtained. By controlling the thickness of the gate dielectric,the threshold voltage ...     

基于聚合物绝缘栅的低电压有机薄膜晶体管

利用甲基丙烯酸甲酯-甲基丙烯酸环氧丙脂为栅绝缘层制备了酞箐铜有机薄膜晶体管,在电压为10V时器件具有较好的性能,栅绝缘层的漏电流密度低至2×10-8A/cm2 。测量其电容特性,该绝缘薄膜的介电常数介于3.9-5.0 。通过对绝缘层的减薄,阈值电压由 -3.5V 升至-2.0V,该酞箐铜有机薄膜晶体管可以在低电压下工作,其场效应迁移率为1.2×10-3 cm2/Vs 。     

High electrical performance liquid-phase HBr oxidation gate insulator of InAlAs/InGaAs metamorphic MOS-mHEMT

The InAlAs/InGaAs metal-oxide-semiconductor metamorphic high electron mobility transistors (MOS-mHEMTs) were demonstrated by using liquid-phase HBr treatment technology to form a high-quality gate insulator layer. In this study, liquid-phase HBr treatment technology was used instead of traditional plasma-assisted chemical vapor deposition (PECVD) because the proposed technology can prevent the device from plasma-induced damage. The novel HBr + ultraviolet (UV) illumination treated InGaAs provided a lower surface states such that MOS structure can be efficiently obtained. Besides, based on the atomic force microscopy (AFM) measurement, the native oxides film formed by HBr + UV illumination treatment also provided a better surface roughness compared to traditional NH₄OH and only HBr treatment solutions. It is beneficial for reducing the surface traps and lowering the leakage current in MOS-mHEMTs. Based on the flicker noise and load-pull power measurement results, HBr + UV treatment mHEMT achieved a low flicker noise at high current level and the power-added efficiency can be enhanced up to 9%. Therefore, the novel liquid phase method of HBr + UV illumination treatment exhibited a highly potential for low noise microwave power device applications.     

Improved enhancement/depletion GaAs MOSFET using anodic oxide as the gate insulator

A GaAs MOSFET with a semi-insulating substrate is described, operating in either the enhancement or the deed depletion modes and showing the highest transconductance reported so far, and a rise time better than 1 ns. The behavior is fully explained by theC/Vcharacteristics of equivalent MOS capacitors.     

High performance a-Si:H thin film transistors based on aluminum gate metallization

We present a systematic study of the sputter deposition conditions for aluminum thin films employed as gate metallization for high performance a-Si:H thin film transistors (TFTs). Here, we vary sputtering parameters such as deposition temperature, process pressure, and power, all of which have a strong bearing on the surface roughness of the film, including hillock generation induced by thermal processing. For example, at a low deposition temperature (30°C) and a low process pressure (5 mTorr), the surface roughness appeared to be significantly reduced. Transistors with gate metallization deposited under these conditions show a low leakage current (10 fA), an ON/OFF ratio better than 10⁸, and a mobility of 1.1 cm²/V s. In contrast, films deposited at 150°C and 10 mTorr, yield a degradation in mobility to 0.77 cm²/V s and an increase in leakage current to 1 pA, caused by the high interface roughness of the TFT channel due to hillock formation on the Al gate.     

Low-temperature (~77 K) properties of InP MOSFETs using anodic-oxide gate insulator

The letter describes advantages of low-temperature (~77 K) operation for InP MOSFETs using an anodic oxide of InP as the gate insulator. By cooling the device to about 100 K, the electron effective mobility in the device is increased by 5?8 times that at room temperature. Moreover, an increasing drift of drain current observed at room temperature disappears completely.