粘贴DNA计算模型的几种分子逻辑门的实现

理论上来说,基于DNA的分子逻辑门是DNA计算机体系结构的产生基础和DNA计算机实现技术的硬件基础。在这篇论文中,我们在先前提出的基于粘贴DNA计算模型的分子逻辑与门的实现方法的基础上,进一步提出了基于粘贴DNA计算模型的分子逻辑或门和与非门的实现方法。与先前方法类似,逻辑门、输入信号和输出信号是DNA分子。可以实现OR,NOT和NAND类型的逻辑门操作。需要使用包括聚合酶链反应(PCR),琼脂糖凝胶电泳,探针的标记与检测等生物工程技术。这些技术集成于DNA芯片中可用于DNA计算机的研制。     

DNA逻辑计算模型的研究现状与展望

DNA计算因其优异的计算能力已经成为当前研究热点,DNA逻辑计算模型是DNA计算体系与运算实现的重要依托。按应用技术将现有DNA逻辑计算模型进行分类：基于链置换的DNA逻辑计算模型、基于核酶的DNA逻辑计算模型、基于G-quadruplex的DNA逻辑计算模型、基于DNA自组装的逻辑计算模型、基于其他分子技术和分子材料的DNA逻辑计算模型。首先阐述了DNA逻辑计算的研究背景和研究目的以及现阶段在生物分子检测、疾病诊断、多因素分析和生物成像等领域的应用并简述其相关概念;然后梳理各DNA逻辑计算模型的研究历史和现状,分析各类逻辑计算模型所应用的分子操控技术和分子材料以及优缺点和应用前景;最后归纳总结DNA逻辑计算领域当前研究热点和发展前景,为未来提出全新的计算方式奠定基础,为信息、医疗等领域提供更好的服务。     

深入浅出DNA分子计算

DNA分子计算技术是人类在计算机缩微化进程中涌现出的一项新技术。追溯到DNA分子计算技术产生的历史背景,介绍了此项技术实现的理论基础,同时与传统电子计算机作比,列举出目前DNA分子计算技术的优劣势所在,并通过解决一个传统货郎担问题的实例,讲述这种基于DNA分子计算技术的生物计算机的工作机制。     

深入浅出DNA分子计算

DNA分子计算技术是人类在计算机缩微化进程中涌现出的一项新技术.追溯到DNA分子计算技术产生的历史背景,介绍了此项技术实现的理论基础,同时与传统电子计算机作比,列举出目前DNA分子计算技术的优劣势所在,并通过解决一个传统货郎担问题的实例,讲述这种基于DNA分子计算技术的生物计算机的工作机制.     

基于压电基因传感器的DNA计算

压电基因传感器是一种新型的生物传感器,它把压电传感器的灵敏性和DNA杂交反应相结合．与传统的基因检测技术相比,它具有结构简单、无需标记、检测时间短、检测信号易处理等特点．将它用于分子运算,与常规的DNA芯片相比,它的检测结果更易于进行自动化处理,因此便于构建大规模的分子运算机器．文中在压电基因传感器和新兴学科DNA计算的基础上,给出了解决0-1规划问题新的DNA计算方法,并指出以前两种基于表面DNA计算在解决这一问题时的不足．与以往的DNA计算方法相比其输出的是电信号,因此具有操作易自动化、识别解更方便和高信息量的优点．与使用常规DNA芯片的表面DNA计算相比,使用压电基因传感器进行DNA计算可以克服可行解识别困难的问题．压电基因传感器技术有望成为新的分子运算工具,可作为构建自动化的DNA计算机的基础．     

DNA计算中的信息安全技术

DNA计算是一种模拟生物分子的结构并借助于分子生物技术进行计算的新模式。它引入了崭新的数据结构和计算方法,为解决NP完全问题提供了全新的途径。由于DNA计算具有信息处理的高并行性、低能耗及高存储密度等优点,对传统的基于计算安全的密码体系提出了挑战。DNA密码便是近年来伴随着DNA计算的研究而出现的密码学新领域。用DNA分子作为信息载体,以实现数据隐藏、认证、加密等安全技术。在简要回顾DNA计算原理的基础上,详细分析了基于DNA的一次一密方案以及Boneh用DNA计算机破解DES的方法;最后探讨在DNA计算中的信息安全技术。     

DNA计算机:原理、进展及难点(Ⅱ)计算机"数据库"的形成--DNA分子的合成问题

基于生化反应机理的DNA计算机模型引起了科学领域内许多不同学科学者们的关注与兴趣．DNA计算已经成为国际科学研究前沿领域内的一个新热点．DNA计算机的研制需要诸如生物工程、计算机科学、数学、物理、化学、信息科学、微电子技术、激光技术以及控制科学等许多学科的共同协作攻关．作者以系列文章的形式拟对DNA计算机的基本原理、研究进展、DNA计算的模型以及当前研究中的难点给予研讨．该文属第二篇,重点讨论DNA计算机研制中DNA分子的合成问题．DNA分子的合成问题不仅是DNA计算中生物操作过程首先要处理的问题,而且是DNA计算机研制中必须要解决的问题,因为最终实用化的DNA计算机应是一种全自动化的．如何将DNA分子的合成过程与编码、其它生化操作自动地衔接起来是全自动化DNA计算机当前研究的关键难题．若要解决这个问题,人们必须很熟悉有关DNA分子合成的基本原理以及合成技术．这也是该文的动机．     

DNA计算机原理、进展及难点(V):DNA分子的固定技术

在DNA计算机的研制中,DNA分子的固定是首先需要处理的一个最为基本的技术问题.事实上,DNA分子的固定技术不仅是生物计算的一个基本技术,而且是整个基因工程、生物芯片,甚至某些疾病诊疗的基础.基于此,文中将对DNA分子的固定技术给予较为系统的研讨,包括基本原理、具体方法等.文中引入了"DNA分子固定系统"的结构体系,并对该结构体系中载体子系统、固定剂子系统、标记子系统这3个主要子系统进行了详细的论述.     

美国科学家成功研制RNA分子生物计算机

目前,美国加州理工学院已研制出一种RNA计算机,它是最先进的生物计算机。克里斯蒂娜·斯默克(Christina Smolke)建立了一个RNA分子装置实现逻辑门的功能,逻辑门是电子计算机的运算基础。     

基于DNA计算的分子下推自动机

DNA分子计算的工作原理是对生物系统进行编码,以生物化学反应为基础,利用生物技术实现生物系统的状态转移来推进计算过程．2001年以色列的Yaakov Benenson等人在基于DNA计算的发卡模型实现了具有状态转移功能的分子有限状态自动机,国内则有利用DNA计算的方法构造可编程分子下推存储器的相关研究．该存储器基于分子自动机的原理,能按一定逻辑进行自组装,是一种纳米尺度的生物存储机构．文中首先通过在分子有限自动机上扩展一个分子下推存储器从而获得了一种简单的分子下推自动机,并基于该下推自动机提出了一类语言的分子自动机解法．接着提出了两种改进的分子下推自动机的模型,通过增加模型复杂度,分别解决了基本型分子下推自动机存在输人字符串限制和输入分子形式不统一的问题．计算理论表明,该种下推自动机的计算能力超过了已有的有限自动机．     

基于FPGA技术的浮点运算器的设计与实现

日趋进步和完善的FPGA(现场可编程门阵列)技术推动了当前数字电路的设计。浮点运算器是计算机的一个组成部件,结构比较复杂,利用FPGA技术设计浮点运算器可以缩短产品的开发周期。介绍了基于FPGA技术的浮点运算器的设计与实现。描述了采用VHDL(VHSIC硬件描述语言)和原理图方式设计完成浮点运算器的方法和步骤。利用FPGA技术,能方便灵活地设计出浮点运算器。     

Construction of quantum gates for concatenated Greenberger–Horne–Zeilinger-type logic qubit

Concatenated Greenberger–Horne–Zeilinger (C-GHZ) state is a kind of logic qubit which is robust in noisy environment. In this paper, we encode the C-GHZ state as the logic qubit and design two kinds of quantum gates for such logic qubit. The first kind is the single logic-qubit gate which contains the logic-qubit bit-flip gate and phase-flip gate. The second kind is the logic-qubit controlled-not (CNOT) gate. We exploit the single quantum gate for physical qubit, such as bit-flip gate and phase-flip gate, and two-qubit CNOT gate to realize the logic-qubit gate. We also calculated the success probability of such logic-qubit gate based on the imperfect physical quantum gate. This protocol may be useful for future quantum computation.     

On security of image ciphers based on logic circuits and chaotic permutations

This paper introduces a cryptanalysis of image encryption techniques that are using chaotic scrambling and logic gates/circuits. Chaotic scrambling, as well as general permutations are considered together with reversible and irreversible gates, including XOR, Toffoli and Fredkin gates. We also investigate ciphers based on chaotic permutations and balanced logic circuits. Except for the implementation of Fredkin’s gate, these ciphers are insecure against chosen-plaintext attacks, no matter whether a permutation is applied globally on the image or via a block-by-block basis. We introduce a new cipher based on chaotic permutations, logic circuits and randomized Fourier-type transforms. The strength of the new cipher is statistically verified with standard statistical encryption measures.     

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.     

Reversible binary subtractor design using quantum dot-cellular automata

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.     

闸门启闭机智能型载荷监控仪的设计与应用

介绍一种以单片机为基础的卷扬式闸门启闭机载荷监控仪的研制,讨论了系统的软、硬件结构和功能特性,着重阐述了单片机及扩展电路、人机接口和通信部分的设计思路和实现方法。     

Specification and initialization of a logic computer system

A logic computer system consists of an inference machine and a compatible logic operating system. This paper describes prospective models for a logic computer system, and its hardware and software components. The language Concurrent Prolog serves as the single implementation, specification, and machine language. The computer system is represented as a logic programming goallogic_computer_system. Specification of the system corresponds to resolution of this goal. Clauses used to solve the goal — and ensuing subgoals — progressively refine the machine, operating system, and computer system designs. In addition, the accumulation of all clauses describing the logic operating system constitute its implementation. Logic computer systems with vastly different fundamental characteristics can be concisely specified in this manner. Two contrasting examples are given and discussed. An important characteristic of both peripheral devices and the overall computer system, whether they are restartable or perpetual, is examined. As well, a method for operational initialization of the logic computer system is presented. The same clauses which incrementally specify characteristics of the computer system also describe the manner in which this initialization takes place.